poster

SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cells

Authors:

Zhe Zhang,

Michael A. Turi,

José G. Delgado-FriasAuthors Info & Claims

GLSVLSI '12: Proceedings of the great lakes symposium on VLSI

Pages 267 - 270

https://doi.org/10.1145/2206781.2206846

Published: 03 May 2012 Publication History

Get Access

Abstract

An in-depth study of the static power consumption in 6T and 8T SRAM cell designs based on 32nm CMOS, FinFET and CNTFET technologies is presented. In addition to the inverter leakage currents, memory cells that are not active when write or read operations occur draw current from/to the bus drivers increasing the total standby power consumption. The FinFET schemes yield substantially lower write (1023.5 pA) and read (522.5 pA) leakage currents in 8T cells, which are 10.4% and 4.4% of the amount in CMOS 8T cells. A CNTFET 6T cell consumes 1.9% and 2.8% of the leakage current drawn by a CMOS 6T cell for write and read.

References

[1]

T-C Chen, "Overcoming Research Challenges for CMOS Scaling: Industry Directions," Int. Conf. on Solid-State and IC Technology, pp. 4--7, Oct. 2006.

Google Scholar

[2]

Int. Technology Roadmap for Semiconductors, www.itrs.net.

Google Scholar

[3]

T. Cakici, K. Kim, and K. Roy, "FinFET Based SRAM Design for Low Standby Power Applications," 8th Int. Symp. on Quality Electronic Design, pp. 127--132, Mar. 2007.

Digital Library

Google Scholar

[4]

Y. B. Kim et al., "New SRAM Cell Design for Low Power and High Reliability Using 32nm Independent Gate FinFET Technology" IEEE Int. Workshop on Design and Test of Nano Devices, Circuits and Systems, pp. 25--28, Sept. 2008.

Digital Library

Google Scholar

[5]

T. King. "FinFETs for nanoscale CMOS digital integrated circuits," Int. Conf. Computer-Aided Design, pp. 207--210, Nov. 2005.

Digital Library

Google Scholar

[6]

D. J. Frank et al., "Device scaling limits of Si MOSFETs and their application dependencies," Proc. of the IEEE, vol. 89, no. 3, pp. 259--288, Mar. 2001.

Crossref

Google Scholar

[7]

P. H-S. Wong, "Field Effect Transistors-from Silicon MOSFETs to Carbon Nanotube FETs," 23rd Int. Conf. on Microelectronics, pp. 103--107, May 2002.

Google Scholar

[8]

B.C. Paul et al., "Impact of a Process Variation on Nanowire and Nanotube Device Performance," IEEE Trans. on Electron Devices, vol. 54, no. 9, pp. 2369--76, Sept. 2007.

Crossref

Google Scholar

[9]

Y. B. Kim et al., "A Low Power 8T SRAM Cell Design Technique for CNTFET," IEEE Int. SoC Design Conf. (ISOCC), pp. 176--179, Nov. 2008.

Google Scholar

[10]

Berkeley Predictive Tech. Model: www.eas.asu.edu/~ptm/.

Google Scholar

[11]

J. G. Fossum et al., "Recent upgrades and applications of UFDG," 2006 NSTI Nanotech. Conf. (Workshop on Compact Modeling), pp. 674--679, May 2006.

Google Scholar

[12]

M. A. Turi and J. G. Delgado-Frias, "Performance-power tradeoffs of 8T FinFET SRAM cells," 54th IEEE Int. Midwest Symp. Circuits Syst., Aug. 2011.

Google Scholar

[13]

CNTFET Models. http://nano.stanford.edu/models.php

Google Scholar

Cited By

View all

Sachdeva AKumar DAbbasian E(2023)A carbon nano-tube field effect transistor based stable, low-power 8T static random access memory cell with improved write access timeAEU - International Journal of Electronics and Communications10.1016/j.aeue.2023.154565162(154565)Online publication date: Apr-2023
https://doi.org/10.1016/j.aeue.2023.154565
Abbasian EOrouji MTaghipour Anvari SAsadi AMahmoodi E(2023)An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technologyInternational Journal of Circuit Theory and Applications10.1002/cta.366751:10(4969-4983)Online publication date: 23-May-2023
https://doi.org/10.1002/cta.3667
Patel PMalik MGupta T(2022)Optimization Techniques for Reliable Low Leakage GNRFET-Based 9T SRAMIEEE Transactions on Device and Materials Reliability10.1109/TDMR.2022.322180622:4(506-516)Online publication date: Dec-2022
https://doi.org/10.1109/TDMR.2022.3221806
Show More Cited By

Index Terms

SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cells
1. Hardware
  1. Hardware validation
  2. Very large scale integration design
    1. VLSI system specification and constraints

Recommendations

Optimization of Leakage Current in SRAM Cell Using Shorted Gate DG FinFET
ACCT '13: Proceedings of the 2013 Third International Conference on Advanced Computing & Communication Technologies

Scaling of conventional CMOS circuit tends to have short channel effects due to which, effect such as drain induced barrier lowering, hot electron effect, punch through etc takes place and hence leakage increases in the transistor. To minimize short ...
Leakage Reduction in 18 nm FinFET based 7T SRAM Cell using Self Controllable Voltage Level Technique
Abstract
As the technology is scaled the power consumption increases significantly, because of which the battery life of portable devices is reduced. Due to high power density, the increased power consumption becomes an obstacle for scaling of devices. ...
Fabrication of Bulk-Si FinFET using CMOS compatible process

A new CMOS (Complementary Metal Oxide Semiconductor) compatible Bulk-Si FinFETs fabrication process has been proposed. Compared with conventional fabrication processes of SOI (Silicon On Insulator) and Bulk-Si FinFETs, this new approach is of low cost ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

GLSVLSI '12: Proceedings of the great lakes symposium on VLSI

May 2012

388 pages

ISBN:9781450312448

DOI:10.1145/2206781

General Chairs:
Erik Brunvard
University of Utah, USA
,
Ken Stevens
University of Utah, USA
,
Program Chairs:
Joseph R. Cavallaro
Rice University, USA
,
Tong Zhang
Rensselaer Polytechnic Institute, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 May 2012

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Poster

Conference

GLSVLSI '12

Sponsor:

SIGDA

GLSVLSI '12: Great Lakes Symposium on VLSI 2012

May 3 - 4, 2012

Utah, Salt Lake City, USA

Acceptance Rates

Overall Acceptance Rate 312 of 1,156 submissions, 27%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

15
Total Citations
View Citations
401
Total Downloads

Downloads (Last 12 months)26
Downloads (Last 6 weeks)2

Reflects downloads up to 27 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Sachdeva AKumar DAbbasian E(2023)A carbon nano-tube field effect transistor based stable, low-power 8T static random access memory cell with improved write access timeAEU - International Journal of Electronics and Communications10.1016/j.aeue.2023.154565162(154565)Online publication date: Apr-2023
https://doi.org/10.1016/j.aeue.2023.154565
Abbasian EOrouji MTaghipour Anvari SAsadi AMahmoodi E(2023)An ultra‐low power and energy‐efficient ternary Half‐Adder based on unary operators and two ternary 3:1 multiplexers in 32‐nm GNRFET technologyInternational Journal of Circuit Theory and Applications10.1002/cta.366751:10(4969-4983)Online publication date: 23-May-2023
https://doi.org/10.1002/cta.3667
Patel PMalik MGupta T(2022)Optimization Techniques for Reliable Low Leakage GNRFET-Based 9T SRAMIEEE Transactions on Device and Materials Reliability10.1109/TDMR.2022.322180622:4(506-516)Online publication date: Dec-2022
https://doi.org/10.1109/TDMR.2022.3221806
Devi MMadhu CGarg NSingh SSingh P(2021)Design and Stability analysis of CNTFET based SRAM cellIOP Conference Series: Materials Science and Engineering10.1088/1757-899X/1033/1/0120431033(012043)Online publication date: 19-Jan-2021
https://doi.org/10.1088/1757-899X/1033/1/012043
Xu DChu KLiu CWang YZhang LLi H(2020)CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive Encoding2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116395(963-966)Online publication date: Mar-2020
https://doi.org/10.23919/DATE48585.2020.9116395
Patel PMalik MGupta T(2020)An ultra-low-power and high-performance SRAM cell design based on GNRFETsInternational Journal of Electronics Letters10.1080/21681724.2020.1794048(1-11)Online publication date: 20-Jul-2020
https://doi.org/10.1080/21681724.2020.1794048
Sun YHe WMao ZJiao HKursun V(2018)Metallic-CN-Removal-Tolerant High-Yield Six-CN-MOSFET SRAM Cell for Carbon-Based Embedded MemoryIEEE Transactions on Electron Devices10.1109/TED.2018.279866765:3(1230-1238)Online publication date: Mar-2018
https://doi.org/10.1109/TED.2018.2798667
Turi MDelgado-Frias J(2017)Full-VDD and near-threshold performance of 8T FinFET SRAM cellsIntegration, the VLSI Journal10.5555/3063717.306372357:C(169-183)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.5555/3063717.3063723
Li AZhao WSong SHunter HMoreno JEmer JSanchez D(2017)BVFProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3123944(532-545)Online publication date: 14-Oct-2017
https://dl.acm.org/doi/10.1145/3123939.3123944
Saxena SMehra R(2017)Low‐power and high‐speed 13T SRAM cell using FinFETsIET Circuits, Devices & Systems10.1049/iet-cds.2016.028711:3(250-255)Online publication date: 17-Jan-2017
https://doi.org/10.1049/iet-cds.2016.0287
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Optimization of Leakage Current in SRAM Cell Using Shorted Gate DG FinFET

Leakage Reduction in 18 nm FinFET based 7T SRAM Cell using Self Controllable Voltage Level Technique

Fabrication of Bulk-Si FinFET using CMOS compatible process