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Architecture support for disciplined approximate programming

Published: 03 March 2012 Publication History

Abstract

Disciplined approximate programming lets programmers declare which parts of a program can be computed approximately and consequently at a lower energy cost. The compiler proves statically that all approximate computation is properly isolated from precise computation. The hardware is then free to selectively apply approximate storage and approximate computation with no need to perform dynamic correctness checks.
In this paper, we propose an efficient mapping of disciplined approximate programming onto hardware. We describe an ISA extension that provides approximate operations and storage, which give the hardware freedom to save energy at the cost of accuracy. We then propose Truffle, a microarchitecture design that efficiently supports the ISA extensions. The basis of our design is dual-voltage operation, with a high voltage for precise operations and a low voltage for approximate operations. The key aspect of the microarchitecture is its dependence on the instruction stream to determine when to use the low voltage. We evaluate the power savings potential of in-order and out-of-order Truffle configurations and explore the resulting quality of service degradation. We evaluate several applications and demonstrate energy savings up to 43%.

References

[1]
Alpha Architecture Handbook, Version 3. Digital Equipment Corporation, 1996.
[2]
C. Alvarez, J. Corbal, and M. Valero. Fuzzy memorization for floating-point multimedia applications. IEEE Trans. Comput., 54 (7), 2005.
[3]
S. Y. Borkar and A. A. Chien. The Aplha 21264 Microprocessor. MICRO, 1999.
[4]
S. Y. Borkar and A. A. Chien. The future of microprocessors. CACM, 54, May 2011.
[5]
L. N. Chakrapani, B. E. S. Akgul, S. Cheemalavagu, P. Korkmaz, K. V. Palem, and B. Seshasayee. Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology. In DATE, 2006.
[6]
C. Chen, A. Srivastava, and M. Sarrafzadeh. On gate level power optimization using dual-supply voltages. IEEE Trans. VLSI Syst., 9, 2001.
[7]
M. Dalton, H. Kannan, and C. Kozyrakis. Raksha: A flexible information flow architecture for software security. In ISCA, 2007.
[8]
M. de Kruijf and K. Sankaralingam. Exploring the synergy of emerging workloads and silicon reliability trends. In SELSE, 2009.
[9]
M. de Kruijf, S. Nomura, and K. Sankaralingam. Relax: An architectural framework for software recovery of hardware faults. In ISCA, 2010.
[10]
D. Ernst, N. S. Kim, S. Das, S. Pant, R. Rao, T. Pham, C. Ziesler, D. Blaauw, T. Austin, K. Flautner, and T. Mudge. Razor: A low-power pipeline based on circuit-level timing speculation. In MICRO, 2003.
[11]
H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, and D. Burger. Dark silicon and the end of multicore scaling. In ISCA, 2011.
[12]
R. Hegde and N. R. Shanbhag. Energy-efficient signal processing via algorithmic noise-tolerance. In ISLPED, 1999.
[13]
J. Howard et al. A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS. In ISSCC, 2010.
[14]
A. Kahng, S. Kang, R. Kumar, and J. Sartori. Designing a processor from the ground up to allow voltage/reliability tradeoffs. In HPCA, 2010.
[15]
W. Kim, D. Brooks, and G.-Y. Wei. A fully-integrated 3-level DC/DC converter for nanosecond-scale DVS with fast shunt regulation. In ISSCC, 2011.
[16]
L. Leem, H. Cho, J. Bau, Q. A. Jacobson, and S. Mitra. ERSA: Error resilient system architecture for probabilistic applications. In DATE, 2010.
[17]
S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In MICRO, 2009.
[18]
X. Li and D. Yeung. Exploiting soft computing for increased fault tolerance. In ASGI, 2006.
[19]
S. Liu, K. Pattabiraman, T. Moscibroda, and B. G. Zorn. Flikker: Saving refresh-power in mobile devices through critical data partitioning. In ASPLOS, 2011.
[20]
H. R. Mahdiani, A. Ahmadi, S. M. Fakhraie, and C. Lucas. Bio-inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications. Trans. Cir. Sys. Part I, 57, 2010.
[21]
N. Muralimanohar, R. Balasubramonian, and N. Jouppi. Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0. In MICRO, 2007.
[22]
S. Narayanan, J. Sartori, R. Kumar, and D. L. Jones. Scalable stochastic processors. In DATE, 2010.
[23]
A. Sampson, W. Dietl, E. Fortuna, D. Gnanapragasam, L. Ceze, and D. Grossman. EnerJ: Approximate data types for safe and general low-power computation. In PLDI, 2011.
[24]
G. E. Suh, J. W. Lee, D. Zhang, and S. Devadas. Secure program execution via dynamic information flow tracking. In ASPLOS, 2004.
[25]
M. Tiwari, H. M. Wassel, B. Mazloom, S. Mysore, F. T. Chong, and T. Sherwood. Complete information flow tracking from the gates up. In ASPLOS, 2009.
[26]
J. Y. F. Tong, D. Nagle, and R. A. Rutenbar. Reducing power by optimizing the necessary precision/range of floating-point arithmetic. IEEE Trans. VLSI Syst., 8 (3), 2000.
[27]
V. Wong and M. Horowitz. Soft error resilience of probabilistic inference applications. In SELSE, 2006.
[28]
Q. Wu, M. Martonosi, D. W. Clark, V. J. Reddi, D. Connors, Y. Wu, J. Lee, and D. Brooks. A dynamic compilation framework for controlling microprocessor energy and performance. In MICRO, 2005.
[29]
C. Yeh, Y.-S. Kang, S.-J. Shieh, and J.-S. Wang. Layout techniques supporting the use of dual supply voltages for cell-based designs. In DAC, 1999.
[30]
H. Zeng, C. S. Ellis, A. R. Lebeck, and A. Vahdat. ECOSystem: Managing energy as a first class operating system resource. In ASPLOS, 2002.

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  • (2024)Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing CircuitsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2023VLP0008E107.A:3(540-548)Online publication date: 1-Mar-2024
  • (2024)Automating application-driven customization of ASIPs: A surveyJournal of Systems Architecture10.1016/j.sysarc.2024.103080148(103080)Online publication date: Mar-2024
  • (2024)Effect of Bit-Size Reduced Half-Precision Floating-Point Format on Image Pixel Characterization for AI ApplicationsResults in Engineering10.1016/j.rineng.2024.103179(103179)Online publication date: Oct-2024
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Information

Published In

cover image ACM SIGPLAN Notices
ACM SIGPLAN Notices  Volume 47, Issue 4
ASPLOS '12
April 2012
453 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/2248487
Issue’s Table of Contents
  • cover image ACM Conferences
    ASPLOS XVII: Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
    March 2012
    476 pages
    ISBN:9781450307598
    DOI:10.1145/2150976
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 March 2012
Published in SIGPLAN Volume 47, Issue 4

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Author Tags

  1. architecture
  2. disciplined approximate computation
  3. energy
  4. power-aware computing

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Cited By

View all
  • (2024)Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing CircuitsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2023VLP0008E107.A:3(540-548)Online publication date: 1-Mar-2024
  • (2024)Automating application-driven customization of ASIPs: A surveyJournal of Systems Architecture10.1016/j.sysarc.2024.103080148(103080)Online publication date: Mar-2024
  • (2024)Effect of Bit-Size Reduced Half-Precision Floating-Point Format on Image Pixel Characterization for AI ApplicationsResults in Engineering10.1016/j.rineng.2024.103179(103179)Online publication date: Oct-2024
  • (2024)A novel approximate cache block compressor for error-resilient image dataComputers and Electrical Engineering10.1016/j.compeleceng.2024.109106115(109106)Online publication date: Apr-2024
  • (2024)Approximate Similarity-Aware Compression for Non-Volatile Main MemoryJournal of Computer Science and Technology10.1007/s11390-023-2565-739:1(63-81)Online publication date: 30-Jan-2024
  • (2024)Approximate Computing ArchitecturesHandbook of Computer Architecture10.1007/978-981-97-9314-3_27(1027-1067)Online publication date: 21-Dec-2024
  • (2023)Dynamic Verification Framework of Approximate Computing Circuits using Quality-Aware Coverage-Based Grey-Box FuzzingIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2022VLP0002E106.A:3(514-522)Online publication date: 1-Mar-2023
  • (2023)Exact and approximate multiplications for signal processing applicationsMicroelectronics Journal10.1016/j.mejo.2023.105688132(105688)Online publication date: Feb-2023
  • (2022)An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant ApproximationIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.316789469:7(2655-2668)Online publication date: Jul-2022
  • (2022)DEVoT: Dynamic Delay Modeling of Functional Units Under Voltage and Temperature VariationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.307697041:4(827-839)Online publication date: Apr-2022
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