Abstract
Power dissipation has become a critical design issue in high performance microprocessors as well as battery powered and wireless electronics, multimedia and digital signal processors, and high speed networking. The most effective way to reduce power consumption is to lower the supply voltage. Reducing the supply voltage, however, increases the circuit delay [596, 598, 627]. The increased delay can be compensated by changing the critical paths with behavioral transformations such as parallelization or pipelining [628]. The resulting circuit consumes less power while satisfying global throughput constraints at the cost of increased circuit area.
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P.-Vaisband, I., Jakushokas, R., Popovich, M., Mezhiba, A.V., Köse, S., Friedman, E.G. (2016). Decoupling Capacitors for Multi-Voltage Power Distribution Systems. In: On-Chip Power Delivery and Management. Springer, Cham. https://doi.org/10.1007/978-3-319-29395-0_42
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