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Externally hazard-free implementations of asynchronous circuits

Authors:

Milton Sawasaki,

Chantal Ykman-Couvreur,

Bill LinAuthors Info & Claims

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Pages 718 - 724

https://doi.org/10.1145/217474.217617

Published: 01 January 1995 Publication History

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Cited By

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Bill Lin (2006)Hierarchical Optimization of Asynchronous Circuits32nd Design Automation Conference10.1109/DAC.1995.250057(712-717)Online publication date: Dec-2006
https://doi.org/10.1109/DAC.1995.250057
Kondratyev ACortadella JKishinevsky MLavagno LYakovlev A(1999)Logic decomposition of speed-independent circuitsProceedings of the IEEE10.1109/5.74002787:2(347-362)Online publication date: Jan-1999
https://doi.org/10.1109/5.740027
Cortadella JKishinevsky MKondratyev ALavagno LYakovlev A(1997)Technology Mapping of Speed-Independent Circuits Based on Combinational Decomposition and ResynthesisProceedings of the 1997 European conference on Design and Test10.5555/787260.787643Online publication date: 17-Mar-1997
https://dl.acm.org/doi/10.5555/787260.787643
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Index Terms

Externally hazard-free implementations of asynchronous circuits
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Buses and high-speed links
  2. Electronic design automation
    1. High-level and register-transfer level synthesis

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The problem of constructing hazard-free Boolean circuits (those avoiding electronic glitches) dates back to the 1940s and is an important problem in circuit design and even in cybersecurity. We show that a DeMorgan circuit, that is, a Boolean AND, OR, NOT ...

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Published In

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

Chairman:
Bryan T. Preas
Xerox Parc, Palo Alto, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 January 1995

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June 12 - 16, 1995

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Bill Lin (2006)Hierarchical Optimization of Asynchronous Circuits32nd Design Automation Conference10.1109/DAC.1995.250057(712-717)Online publication date: Dec-2006
https://doi.org/10.1109/DAC.1995.250057
Kondratyev ACortadella JKishinevsky MLavagno LYakovlev A(1999)Logic decomposition of speed-independent circuitsProceedings of the IEEE10.1109/5.74002787:2(347-362)Online publication date: Jan-1999
https://doi.org/10.1109/5.740027
Cortadella JKishinevsky MKondratyev ALavagno LYakovlev A(1997)Technology Mapping of Speed-Independent Circuits Based on Combinational Decomposition and ResynthesisProceedings of the 1997 European conference on Design and Test10.5555/787260.787643Online publication date: 17-Mar-1997
https://dl.acm.org/doi/10.5555/787260.787643
Cortadella JKishinevsky MKondratyev ALavagno LYakovlev A(1997)Technology mapping of speed-independent circuits based on combinational decomposition and resynthesisProceedings European Design and Test Conference. ED & TC 9710.1109/EDTC.1997.582340(98-105)Online publication date: 1997
https://doi.org/10.1109/EDTC.1997.582340
Kondratyev ACortadella JKishinevsky MLavagno LYakovlev A(1997)Technology mapping for speed-independent circuits: Decomposition and resynthesisProceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems10.1109/ASYNC.1997.587178(240-253)Online publication date: 1997
https://doi.org/10.1109/ASYNC.1997.587178
Lin Bde Jong GKolks TPreas B(1995)Hierarchical optimization of asynchronous circuitsProceedings of the 32nd annual ACM/IEEE Design Automation Conference10.1145/217474.217616(712-717)Online publication date: 1-Jan-1995
https://dl.acm.org/doi/10.1145/217474.217616
Ykman-Couvreur CLin B(1995)Optimised state assignment for asynchronous circuit synthesisProceedings Second Working Conference on Asynchronous Design Methodologies10.1109/WCADM.1995.514649(118-127)Online publication date: 1995
https://doi.org/10.1109/WCADM.1995.514649
Ykman-Couvreur CLin B(1995)Efficient state assignment framework for asynchronous state graphsProceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors10.1109/ICCD.1995.528943(692-697)Online publication date: 1995
https://doi.org/10.1109/ICCD.1995.528943

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Designing Asynchronous Circuits using NULL Convention Logic (NCL)

Notes on Hazard-Free Circuits