Skip header Section
Skip Bibliometrics Section
Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete SystemsJanuary 1990
- Authors:
- M. A. Kishinevskiµi,
- Alexandre V. Yakovlev,
- Editor:
- Victor I. Varshavsky
Abstract
No abstract available.
Cited By
- Stepchenkov Y, Diachenko Y, Zakharov V, Rogdestvenski Y, Morozov N and Stepchenkov D Quasi-delay-insensitive computing device Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation, (276-285)
- Shang D, Yakovlev A, Koelmans A, Sokolov D and Bystrov A (2019). Registers for phase difference based logic, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15:6, (720-724), Online publication date: 1-Jun-2007.
- Ruan J, Wang Z, Dai K and Li Y Design and test of self-checking asynchronous control circuit Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation, (320-329)
- Toms W and Edwards D Efficient synthesis of speed-independent combinational logic circuits Proceedings of the 2005 Asia and South Pacific Design Automation Conference, (1022-1026)
- Efthymiou A, Bainbridge J and Edwards D (2005). Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13:12, (1384-1393), Online publication date: 1-Dec-2005.
- Silver S and Brzozowski J (2019). True Concurrency in Models of Asynchronous Circuit Behavior, Formal Methods in System Design, 22:3, (183-203), Online publication date: 1-May-2003.
- Josephs M and Furey D Delay-insensitive interface specification and synthesis Proceedings of the conference on Design, automation and test in Europe, (169-175)
- Liebelt M and Burgess N (1999). Detecting Exitory Stuck-At Faults in Semimodular Asynchronous Circuits, IEEE Transactions on Computers, 48:4, (442-448), Online publication date: 1-Apr-1999.
- Brunvand E, Nowick S and Yun K Practical advances in asynchronous design and in asynchronous/synchronous interfaces Proceedings of the 36th annual ACM/IEEE Design Automation Conference, (104-109)
- Saarepera M and Yoneda T A Self-Timed Implementation of Boolean Functions Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
- Yakovlev A (2019). Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets, Formal Methods in System Design, 12:1, (39-71), Online publication date: 1-Jan-1998.
- Cortadella J, Kishinevsky M, Kondratyev A, Lavagno L, Pastor E and Yakovlev A Decomposition and technology mapping of speed-independent circuits using Boolean relations Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, (220-227)
- Cortadella J, Kishinevsky M, Kondratyev A, Lavagno L and Yakovlev A Technology Mapping of Speed-Independent Circuits Based on Combinational Decomposition and Resynthesis Proceedings of the 1997 European conference on Design and Test
- Varshavsky V and Marakhovsky V Global Synchronization of Asynchronous Arrays in Logical Time Proceedings of the 2nd AIZU International Symposium on Parallel Algorithms / Architecture Synthesis
- Kolks T, Vercauteren S and Lin B Control Resynthesis for Control-Dominated Asynchronous Designs Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
- Beerel P, Yun K and Chou W Optimizing average-case delay in technology mapping of burst-mode circuits Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
- Lin B, de Jong G and Kolks T Hierarchical optimization of asynchronous circuits Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, (712-717)
- Sawasaki M, Ykman-Couvreur C and Lin B Externally hazard-free implementations of asynchronous circuits Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, (718-724)
- de Jong G and Lin B A communicating Petri net model for the design of concurrent asynchronous modules Proceedings of the 31st annual Design Automation Conference, (49-55)
- Kondratyev A, Kishinevsky M, Lin B, Vanbekbergen P and Yakovlev A Basic gate implementation of speed-independent circuits Proceedings of the 31st annual Design Automation Conference, (56-62)
- Nielsen C Evaluation of function blocks for asynchronous design Proceedings of the conference on European design automation, (454-459)
- Lavagno L, Keutzer K and Sangiovanni-Vincentelli A Algorithms for synthesis of hazard-free asynchronous circuits Proceedings of the 28th ACM/IEEE Design Automation Conference, (302-308)
Please enable JavaScript to view thecomments powered by Disqus.
Recommendations
Optimization of NULL convention self-timed circuits
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within the NULL Convention Logic (NCL) paradigm. NCL logic functions are realized using 27 distinct transistor networks implementing the set of all functions of ...
Self-Timed Carry-Lookahead Adders
Special issue on computer arithmeticInteger addition is one of the most important operations in digital computer systems because the performance of processors is significantly influenced by the speed of their adders. This paper proposes a self-timed carry-lookahead adder in which the ...
A pulse-to-static conversion latch with a self-timed control circuit
ICCD '97: Proceedings of the 1997 International Conference on Computer Design (ICCD '97)The design and experimental demonstration of a low-power pulse-to-static conversion latch circuit is described. The circuit includes self-timed control and a 64-bit latch array, both designed utilizing self-resetting CMOS (SRCMOS) circuit techniques. ...