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On synthesis-for-testability of combinational logic circuits

Authors:

Irith Pomeranz,

Sudhakar M. ReddyAuthors Info & Claims

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Pages 126 - 132

https://doi.org/10.1145/217474.217518

Published: 01 January 1995 Publication History

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Cited By

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Wang NPomeranz IReddy SSinha AVenkataraman S(2019)Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based DesignACM Transactions on Design Automation of Electronic Systems10.1145/332506624:4(1-19)Online publication date: 29-May-2019
https://dl.acm.org/doi/10.1145/3325066
Pomeranz IReddy S(2008)Synthesis for Broadside Testability of Transition FaultsProceedings of the 26th IEEE VLSI Test Symposium10.1109/VTS.2008.10(221-226)Online publication date: 27-Apr-2008
https://dl.acm.org/doi/10.1109/VTS.2008.10
Pomeranz IReddy S(2008)Design-for-Testability for Improved Path Delay Fault Coverage of Critical PathsProceedings of the 21st International Conference on VLSI Design10.1109/VLSI.2008.22(175-180)Online publication date: 4-Jan-2008
https://dl.acm.org/doi/10.1109/VLSI.2008.22
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On synthesis-for-testability of combinational logic circuits
1. Hardware

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Published In

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

Chairman:
Bryan T. Preas
Xerox Parc, Palo Alto, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 January 1995

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June 12 - 16, 1995

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Cited By

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Wang NPomeranz IReddy SSinha AVenkataraman S(2019)Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based DesignACM Transactions on Design Automation of Electronic Systems10.1145/332506624:4(1-19)Online publication date: 29-May-2019
https://dl.acm.org/doi/10.1145/3325066
Pomeranz IReddy S(2008)Synthesis for Broadside Testability of Transition FaultsProceedings of the 26th IEEE VLSI Test Symposium10.1109/VTS.2008.10(221-226)Online publication date: 27-Apr-2008
https://dl.acm.org/doi/10.1109/VTS.2008.10
Pomeranz IReddy S(2008)Design-for-Testability for Improved Path Delay Fault Coverage of Critical PathsProceedings of the 21st International Conference on VLSI Design10.1109/VLSI.2008.22(175-180)Online publication date: 4-Jan-2008
https://dl.acm.org/doi/10.1109/VLSI.2008.22
Pomeranz IKundu SReddy S(2004)Masking of Unknown Output Values during Output Response Compression byUsing Comparison UnitsIEEE Transactions on Computers10.1109/TC.2004.125579453:1(83-88)Online publication date: 1-Jan-2004
https://dl.acm.org/doi/10.1109/TC.2004.1255794
Ohtake SOhtani KFujiwara H(2003)A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation AlgorithmsProceedings of the conference on Design, Automation and Test in Europe - Volume 110.5555/789083.1022743Online publication date: 3-Mar-2003
https://dl.acm.org/doi/10.5555/789083.1022743
Pomeranz IReddy S(2002)Test Enrichment for Path Delay Faults Using Multiple Sets of Target FaultsProceedings of the conference on Design, automation and test in Europe10.5555/882452.874407Online publication date: 4-Mar-2002
https://dl.acm.org/doi/10.5555/882452.874407
Pomeranz IKundu SReddy SAckland B(2002)On output response compression in the presence of unknown output valuesProceedings of the 39th annual Design Automation Conference10.1145/513918.513985(255-258)Online publication date: 10-Jun-2002
https://dl.acm.org/doi/10.1145/513918.513985
Ohtake SMiwa SFujiwara H(2002)A method of test generation for path delay faults in balanced sequential circuitsProceedings 20th IEEE VLSI Test Symposium (VTS 2002)10.1109/VTS.2002.1011160(321-327)Online publication date: 2002
https://doi.org/10.1109/VTS.2002.1011160
Pomeranz IReddy S(2002)Test enrichment for path delay faults using multiple sets of target faultsProceedings 2002 Design, Automation and Test in Europe Conference and Exhibition10.1109/DATE.2002.998379(722-729)Online publication date: 2002
https://doi.org/10.1109/DATE.2002.998379
Pomeranz IKundu SReddy S(2002)On output response compression in the presence of unknown output valuesProceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)10.1109/DAC.2002.1012631(255-258)Online publication date: 2002
https://doi.org/10.1109/DAC.2002.1012631
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