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A first step towards automatic application of power analysis countermeasures

Published: 05 June 2011 Publication History

Abstract

In cryptography, side channel attacks, such as power analysis, attempt to uncover secret information from the physical implementation of cryptosystems rather than exploiting weaknesses in the cryptographic algorithms themselves. The design and implementation of physically secure cryptosystems is a challenge for both hardware and software designers. Measuring and evaluating the security of a system is manual and empirical, which is costly and time consuming; this work demonstrates that it is possible to automate these processes. We introduce a systematic methodology for automatic application of software countermeasures and demonstrate its effectiveness on an AES software implementation running on an 8-bit AVR microcontroller. The framework identifies the most vulnerable instructions of the implementation to power analysis attacks, and then transforms the software using a chosen countermeasure to protect the vulnerable instructions. Lastly, it evaluates the security of the system using an information-theoretic metric and a direct attack.

References

[1]
C. Archambeau, E. Peeters, F.-X. Standaert and J.-J. Quisquater. Template attacks in principal subspaces. In Cryptographic Hardware and Embedded Systems --CHES 2006, pages 1--14, 2006.
[2]
M. Barbosa, A. Moss, and D. Page. Constructive and destructive use of compilers in elliptic curve cryptography. Journal of Cryptology, 22(2):259--281, April 2009.
[3]
Computer Aided Cryptography Engineering (CACE European Project). http://www.cace-project.eu.
[4]
J.-S. Coron and L. Goubin. On Boolean and arithmetic masking against differential power analysis. In Cryptographic Hardware and Embedded Systems --CHES 2000, pages 231--237, 2000.
[5]
K. Gandolfi, C. Mourtel, and F. Olivier. Electromagnetic analysis: Concrete results. In Cryptographic Hardware and Embedded Systems --CHES 2001, pages 251--261, May 2001.
[6]
S. Guilley, P. Hoogvorst, Y. Mathieu, and R. Pacalet. The "backend duplication" method. In Cryptographic Hardware and Embedded Systems --CHES 2005, pages 383--397, August 2005.
[7]
J. Irwin, D. Page, and N. P. Smart. Instruction stream mutation for non-deterministic processors. In 13th International Conference on Application-Specific Systems, Architectures and Processors, pages 286--295, July 2002.
[8]
P. Kocher. Timing attacks on implementations of Diffie-Hellman, RSA, DSS and other systems. In Advances in Cryptology --CRYPTO '96, pages 104--113, September 1996.
[9]
P. Kocher, J. Jaffe, and B. Jun. Differential power analysis. In Advances in Cryptology --CRYPTO '99, pages 398--412, August 1999.
[10]
S. Mangard, E. Oswald, and T. Popp. Power Analysis Attacks - Revealing the Secrets of Smart Cards. Springer, 2007.
[11]
D. May, H. L. Muller, and N. P. Smart. Non-deterministic processors. In Information Security and Privacy - ACISP '01, pages 115--129, July 2001.
[12]
D. May, H. L. Muller, and N. P. Smart. Random register renaming to foil DPA. In Cryptographic Hardware and Embedded Systems --CHES 2001, pages 28--38, May 2001.
[13]
S. W. Moore, R. D. Mullins, P. A. Cunningham, R. J. Anderson, and G. S. Taylor. Improving smart card security using self-timed circuits. In 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems - ASYNC 2002, pages 211--218, April 2002.
[14]
E. Prouff. DPA Attacks and S-Boxes. In Fast Software Encryption --FSE 2005, pages 424--441, 2005.
[15]
F. Regazzoni, A. Cevrero, F.-X. Standaert, S. Badel, T. Kluter, P. Brisk, Y. Leblebici, and P. Ienne. A design flow and evaluation framework for DPA-resistant instruction set extensions. In Cryptographic Hardware and Embedded Systems --CHES 2009, pages 205--219, September 2009.
[16]
F. Regazzoni, T. Eisenbarth, A. Poschmann, J. Großschädl, F. K. Gürkaynak, M. Macchetti, Z. T. Deniz, L. Pozzi, C. Paar, Y. Leblebici, and P. Ienne. Evaluating resistance of MCML technology to power analysis attacks using a simulation-based methodology. Transactions on Computational Science, 5430:230--243, 2009.
[17]
A. G. Rostovtsev and O. V. Shemyakina. AES side channel attack protection using random isomorphisms. Cryptology e-Print Archive, March 2005.
[18]
F.-X. Standaert, T. G. Malkin, and M. Yung. A unified framework for the analysis of side-channel key recovery attacks. In Advances in Cryptology --EUROCRYPT '09, pages 443--461, April 2009.
[19]
S. Tillich and J. Großschädl. Power analysis resistant AES implementation with instruction set extensions. In Cryptographic Hardware and Embedded Systems --CHES 2007, pages 303--319, 2007.
[20]
K. Tiri, M. Akmal, and I. Verbauwhede. A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards. In 28th European Solid-State Circuits Conference, pages 403--406, September 2002.
[21]
K. Tiri and I. Verbauwhede. A digital design flow for secure integrated circuits. IEEE Transactions on CAD of Integrated Circuits and Systems, 25(7):1197--1208, 2006.
[22]
S. S. R. Varadhan. Large deviations. Annals of Probability, 36(2):397--419, 2008.

Cited By

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  • (2024)Compositional Verification of First-Order Masking Countermeasures against Power Side-Channel AttacksACM Transactions on Software Engineering and Methodology10.1145/363570733:3(1-38)Online publication date: 14-Mar-2024
  • (2023)Compositional Verification of Efficient Masking Countermeasures against Side-Channel AttacksProceedings of the ACM on Programming Languages10.1145/36228627:OOPSLA2(1817-1847)Online publication date: 16-Oct-2023
  • (2023)Emulating Side Channel Attacks on gem5: lessons learned2023 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW)10.1109/EuroSPW59978.2023.00036(287-295)Online publication date: Jul-2023
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Published In

cover image ACM Conferences
DAC '11: Proceedings of the 48th Design Automation Conference
June 2011
1055 pages
ISBN:9781450306362
DOI:10.1145/2024724
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 05 June 2011

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Author Tags

  1. AVR
  2. automation
  3. power analysis attacks
  4. software countermeasure

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Cited By

View all
  • (2024)Compositional Verification of First-Order Masking Countermeasures against Power Side-Channel AttacksACM Transactions on Software Engineering and Methodology10.1145/363570733:3(1-38)Online publication date: 14-Mar-2024
  • (2023)Compositional Verification of Efficient Masking Countermeasures against Side-Channel AttacksProceedings of the ACM on Programming Languages10.1145/36228627:OOPSLA2(1817-1847)Online publication date: 16-Oct-2023
  • (2023)Emulating Side Channel Attacks on gem5: lessons learned2023 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW)10.1109/EuroSPW59978.2023.00036(287-295)Online publication date: Jul-2023
  • (2022)A generalized approach to estimation of memoryless covert channel information leakage capacityArray10.1016/j.array.2022.10013114(100131)Online publication date: Jul-2022
  • (2021)A Hybrid Approach to Formal Verification of Higher-Order Masked Arithmetic ProgramsACM Transactions on Software Engineering and Methodology10.1145/342801530:3(1-42)Online publication date: 11-Feb-2021
  • (2021)Side-Channel Propagation Measurements and Modeling for Hardware Security in IoT DevicesIEEE Transactions on Antennas and Propagation10.1109/TAP.2020.303765969:6(3470-3484)Online publication date: Jun-2021
  • (2021)Compiler-Assisted Hardening of Embedded Software Against Interrupt Latency Side-Channel Attacks2021 IEEE European Symposium on Security and Privacy (EuroS&P)10.1109/EuroSP51992.2021.00050(667-682)Online publication date: Sep-2021
  • (2020)Remote Monitoring and Propagation Modeling of EM Side-Channel Signals for IoT Device Security2020 14th European Conference on Antennas and Propagation (EuCAP)10.23919/EuCAP48036.2020.9135387(1-5)Online publication date: Mar-2020
  • (2020)SCRIPTACM Transactions on Design Automation of Electronic Systems10.1145/338344525:3(1-27)Online publication date: 13-May-2020
  • (2020)Formal Verification of Masking Countermeasures for Arithmetic ProgramsIEEE Transactions on Software Engineering10.1109/TSE.2020.3008852(1-1)Online publication date: 2020
  • Show More Cited By

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