chapter

Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology

Authors:

Francesco Regazzoni,

Thomas Eisenbarth,

Axel Poschmann,

Johann Großschädl,

Frank Gurkaynak,

Marco Macchetti,

Yusuf Leblebici,

Paolo IenneAuthors Info & Claims

Transactions on Computational Science IV: Special Issue on Security in Computing

March 2009

Pages 230 - 243

https://doi.org/10.1007/978-3-642-01004-0_13

Published: 27 March 2009 Publication History

Abstract

This paper explores the resistance of MOS Current Mode Logic (MCML) against attacks based on the observation of the power consumption. Circuits implemented in MCML, in fact, have unique characteristics both in terms of power consumption and the dependency of the power profile from the input signal pattern. Therefore, MCML is suitable to protect cryptographic hardware from Differential Power Analysis and similar side-channel attacks.

In order to demonstrate the effectiveness of different logic styles against power analysis attacks, two full cores implementing the AES algorithm were realized and implemented with CMOS and MCML technology, and a set of different types of attack was performed using power traces derived from SPICE-level simulations. Although all keys were discovered for CMOS, MCML traces did not presents characteristic that can lead to a successful attack.

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Cited By

Bucci MGiancane LLuzzi RTrifiletti A(2018)A flip-flop for the DPA resistant three-phase dual-rail pre-charge logic familyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.216586220:11(2128-2132)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2011.2165862
Bayrak ARegazzoni FBrisk PStandaert FIenne PStok LDutt NHassoun S(2011)A first step towards automatic application of power analysis countermeasuresProceedings of the 48th Design Automation Conference10.1145/2024724.2024778(230-235)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1145/2024724.2024778
Regazzoni FCevrero AStandaert FBadel SKluter TBrisk PLeblebici YIenne P(2009)A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set ExtensionsProceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems10.1007/978-3-642-04138-9_15(205-219)Online publication date: 30-Aug-2009
https://dl.acm.org/doi/10.1007/978-3-642-04138-9_15

Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology
1. Hardware

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Information & Contributors

Information

Published In

cover image Guide books

Transactions on Computational Science IV: Special Issue on Security in Computing

March 2009

262 pages

ISBN:9783642010033

Editors:
Marina L. Gavrilova
Department of Computer Science, University of Calgary, Calgary, Canada T2N 1N4
,
C. J. Tan
OptimaNumerics Ltd., Belfast, UK BT1 2DX
,
Edward David Moreno
University of Amazonas State - UEA Manaus, Brazil

Publisher

Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 27 March 2009

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Cited By

Bucci MGiancane LLuzzi RTrifiletti A(2018)A flip-flop for the DPA resistant three-phase dual-rail pre-charge logic familyIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.216586220:11(2128-2132)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1109/TVLSI.2011.2165862
Bayrak ARegazzoni FBrisk PStandaert FIenne PStok LDutt NHassoun S(2011)A first step towards automatic application of power analysis countermeasuresProceedings of the 48th Design Automation Conference10.1145/2024724.2024778(230-235)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1145/2024724.2024778
Regazzoni FCevrero AStandaert FBadel SKluter TBrisk PLeblebici YIenne P(2009)A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set ExtensionsProceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems10.1007/978-3-642-04138-9_15(205-219)Online publication date: 30-Aug-2009
https://dl.acm.org/doi/10.1007/978-3-642-04138-9_15

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