Nothing Special   »   [go: up one dir, main page]

skip to main content
research-article

An adaptive write buffer management scheme for flash-based SSDs

Published: 24 February 2012 Publication History

Abstract

Solid State Drives (SSD's) have shown promise to be a candidate to replace traditional hard disk drives. The benefits of SSD's over HDD's include better durability, higher performance, and lower power consumption, but due to certain physical characteristics of NAND flash, which comprise SSD's, there are some challenging areas of improvement and further research. We focus on the layout and management of the small amount of RAM that serves as a cache between the SSD and the system that uses it. Of the techniques that have previously been proposed to manage this cache, we identify several sources of inefficient cache space management due to the way pages are clustered in blocks and the limited replacement policy. We find that in many traces hot pages reside in otherwise cold blocks, and that the spatial locality of most clusters can be fully exploited in a limited time period, so we develop a hybrid page/block architecture along with an advanced replacement policy, called BPAC, or Block-Page Adaptive Cache, to exploit both temporal and spatial locality. Our technique involves adaptively partitioning the SSD on-disk cache to separately hold pages with high temporal locality in a page list and clusters of pages with low temporal but high spatial locality in a block list. In addition, we have developed a novel mechanism for flash-based SSD's to characterize the spatial locality of the disk I/O workload and an approach to dynamically identify the set of low spatial locality clusters. We run trace-driven simulations to verify our design and find that it outperforms other popular flash-aware cache schemes under different workloads. For instance, compared to a popular flash aware cache algorithm BPLRU, BPAC reduces the number of cache evictions by up to 79.6% and 34% on average.

References

[1]
Agrawal, N., Prabhakaran, V., Wobber, T., Davis, J. D., Manasse, M., and Panigrahy, R. 2008. Design tradeoffs for SSD performance. In Proceedings of the USENIX 2008 Annual Technical Conference on Annual Technical Conference.
[2]
Balakrishnan, M., Kadav, A., Prabhakaran, V., and Malkhi, D. 2010. Differential RAID: Rethinking RAID for SSD reliability. ACM Trans. Storage 6, 2, 1--22.
[3]
Bansal, S. and Modha, D. S. 2004. CAR: Clock with Adaptive Replacement. In Proceedings of the 3rd USENIX Conference on File and Storage Technologies (FAST'04). 187--200.
[4]
Bez, R., Camerlenghi, E., Modelli, A., and Visconti, A. 2003. Introduction to flash memory. Proc. IEEE 91, 489--502.
[5]
Chang, Y., Lin, J., Hsieh, J., and Kuo, T. 2010. A strategy to emulate NOR flash with NAND flash. ACM Trans. Storage 6, 2, 1--23.
[6]
Chang, Y.-H., Hsieh, J.-W., and Kuo, T.-W. 2007. Endurance enhancement of flash-memory storage systems: An efficient static wear leveling design. In Proceedings of the IEEE/ACM Design Automation Conference (DAC).
[7]
Chen, F., Lee, R., and Zhang, X. 2011. Essential roles of exploiting internal parallelism of flash memory based solid state drives in high-speed data processing. In Proceedings of the 17th IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE.
[8]
Eetimes. 2010. http://www.eetimes.com/electronics-news/4207194/Toshiba_rolls_24_nm_NAND_flash.
[9]
Engadet. http://www.engadget.com/2010/04/19/.
[10]
Gill, B. S. and Modha, D. S. 2005. WOW: Wise Ordering For Writes---Combining spatial and temporal locality in non-volatile caches. In Proceedings of the 4th Conference on USENIX Conference on File and Storage Technologies (FAST'05). USENIX Association, Berkeley, CA.
[11]
Gupta, A., Kim, Y., and Urgaonkar, B. 2009. DFTL: A flash translation layer employing demand-based selective caching of page-level address mappings. In Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'09). ACM, New York, 229--240.
[12]
Gupta, A., Pisolkar, R., Urgaonkar, B., and Sivasubramaniam, A. 2011. Leveraging value locality in optimizing NAND flash-based SSDs. In Proceedings of the 9th USENIX Conference on File and Stroage Technologies. USENIX Association.
[13]
Hat, R. 2010. The journalling flash file system, version 2. http://sourceware.org/jffs2/.
[14]
Hewlett-Packard Laboratories. cello99 traces. http://tesla.hpl.hp.com/opensource/.
[15]
Hu, J., Jiang, H., Tian, L., and Xu, L. 2010. PUD-LRU: An erase-efficient write buffer management algorithm for flash memory SSD. In Proceedings of the International Symposium on Modeling, Analysis, and Simulation of Computer Systems. 69--78.
[16]
Hutsell, W., Bowen, J., and Ekker, N. 2008. Flash solid-state disk reliability. Tech. rep.
[17]
Intel. 2009. Intel X25-M SATA Solid State Drive. http://download.intel.com/design/flash/nand/mainstream/322296.pdf.
[18]
Intel. 2010. http://www.intel.com/pressroom/archive/releases/20100201comp.htm.
[19]
Jiang, S., Ding, X., Chen, F., Tan, E., and Zhang, X. 2005. DULO: An effective buffer cache management scheme to exploit both temporal and spatial locality. In Proceedings of the 4th Conference on USENIX Conference on File and Storage Technologies (FAST'05). USENIX Association, Berkeley, CA.
[20]
Jiang, S. and Zhang, X. 2002. LIRS: An efficient low inter-reference recency set replacement policy to improve buffer cache performance. In Proceedings of the ACM SIGMATRICS International Conference Measurement and Modeling of Computer Systems, 31--42.
[21]
Jo, H., Kang, J.-U., Park, S.-Y., Kim, J.-S., and Lee, J. 2006. FAB: Flash-Aware Buffer management policy for portable media players. IEEE Trans. Consum. Elect. 52, 2, 485--493.
[22]
Johnson, T. and Shasha, D. 1994. 2Q: A low overhead high performance buffer management replacement algorithm. In Proceedings of the 20th International Conference on Very Large Data Bases (VLDB'94). Morgan Kaufmann Publishers Inc., San Francisco, CA, 439--450.
[23]
Josephson, W., Bongo, L., Li, K., and Flynn, D. 2010. DFS: A file system for virtualized flash storage. ACM Trans. Storage 6, 3, 1--25.
[24]
Jung, J., Won, Y., Kim, E., Shin, H., and Jeon, B. 2010. FRASH: Exploiting storage class memory in hybrid file system for hierarchical storage. ACM Trans. Storage 6, 1, 1--25.
[25]
Kang, J. U., Jo, H., Kim, J. S., and Lee, J. 2006. A superblock-based flash translation layer for nand flash memory. In Proceedings of the International Conference on Embedded Software.
[26]
Kang, S., Park, S., Jung, H., Shim, H., and Cha, J. 2009. Performance trade-offs in using NVRAM write buffer for flash memory-based storage devices. IEEE Trans. Comput. 58, 6, 744--758.
[27]
Karedla, R., Love, J. S., and Wherry, B. G. 1994. Caching strategies to improve disk system performance. IEEE Comput. 27, 3, 38--46.
[28]
Kim, H. and Ahn, S. 2008. BPLRU: A buffer management scheme for improving random writes in flash storage abstract. In Proceedings of 6th USENIX Conference on File and Storage Technologies (FAST'08).
[29]
Kim, J. M., Choi, J., Kim, J., Noh, S. H., Min, S. L., Cho, Y., and Kim, C. S. 2000. A low-overhead, high-performance unified buffer management scheme that exploits sequential and looping references. In Proceedings of the 4th Symposium on Operating System Design and Implementation (OSDI'00). 119--134.
[30]
Kim, J., Kim, J. M., Noh, S., Min, S. L., and Cho, Y. 2002. A space-efficient flash translation layer for compactflash systems. IEEE Trans. Consum. Electron. 48, 2, 366--375.
[31]
Lee, D., Choi, J., Kim, J., Noh, S., Min, S., Cho, Y., and Kim, C. 2001. LRFU: A spectrum of policies that subsumes the least recently used and least frequently used policies. IEEE Trans. Comput. 50, 12, 1352--1361.
[32]
Lee, S., Ha, K., Zhang, K., Kim, J., and Kim, J. 2009. FlexFS: A flexible flash file system for MLC NAND flash memory. In Proceedings of the USENIX Annual Technical Conference. USENIX.
[33]
Lee, S., Shin, D., Kim, Y.-J., and Kim, J. 2008. LAST: Locality-aware sector translation for NAND flash memory-based storage systems. SIGOPS Oper. Syst. Rev. 42, 6, 36--42.
[34]
Lee, S.-W., Park, D.-J., Chung, T.-S., Lee, D.-H., Park, S.-W., and Song, H.-J. 2005. FAST: An FTL scheme with fully associative sector translations. In Proceedings of the UKC Conference. UKC.
[35]
Lee, Y.-G., Jung, D., Kang, D., and Kim, J.-S. 2008. uFTL: a memory-efficient flash translation layer supporting multiple mapping granularities. In Proceedings of the 8th ACM International Conference on Embedded Software (EMSOFT'08). ACM, New York, 21--30.
[36]
Manning, C. 2010. Yet another flash file system. http://www.yaffs.net/.
[37]
Mason, L. 2009. Rethinking SSDs. http://www.denali.com/wordpress/index.php/dmr/2009/07/23/rethinking-ssds.
[38]
Megiddo, N. and Modha, D. 2003. ARC: A self-tuning, low overhead replacement cache. In Proceedings of the 2nd USENIX Conference on File and Storage Technologies (FAST'03). 115--130.
[39]
Megiddo, N. and Modha, D. S. 2004. Outperforming LRU with an adaptive replacement cache algorithm. Computer 37, 4, 58--65.
[40]
Newegg. 2009a. Intel X25-M Mainstream SSDSA2MH160G2C1 2.5-inch160GB SATA II MLC Internal Solid state disk (SSD). http://www.newegg.com/Product/Product.aspx?Item=N82E16820167017.
[41]
Newegg. 2009b. Western Digital VelociRaptor WD3000HLFS 300GB 10000 RPM 16MB cache SATA 3.0Gb/s 3.5-inch internal hard drive---OEM. http://www.newegg.com/Product/Product.aspx?Item= N82E16822136322.
[42]
Nicola, V., Dan, A., and Dias, D. 1992. Analysis of the generalized clock buffer replacement scheme for database transaction processing. In Proceedings of the ACM SIGMETRICS Joint International Conference on Measurement and Modeling of Computer Systems. ACM, 35--46.
[43]
O'Neil, E. J., O'Neil, P. E., and Weikum, G. 1993. The LRU-K page replacement algorithm for database disk buffering. In Proceedings of the ACM SIGMOD International Conference on Management of Data (SIGMOD'93). ACM, New York, 297--306.
[44]
ONFI. 2010. http://onfi.org/.
[45]
Park, S.-Y., Jung, D., Kang, J.-U., Kim, J.-S., and Lee, J. 2006. CFLRU: A replacement algorithm for flash memory. In Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES'06). ACM, New York, 234--241.
[46]
Ren, J. and Yang, Q. 2011. I-CASH: Intelligently Coupled Array of SSD and HDD. In Proceedings of the 17th IEEE International Symposium on High Performance Computer Architecture (HPCA).
[47]
Rosenblum, M. and Ousterhout, J. K. 1992. The design and implementation of a log-structured file system. ACM Trans. Comput. Syst. 10, 1, 26--52.
[48]
Samsung. 2010. http://www.samsung.com/global/business/semiconductor/products/fusionmemory/Products-OneNAND.html.
[49]
Shim, H., Seo, B.-K., Kim, J.-S., and Maeng, S. 2010. An adaptive partitioning scheme for DRAM-based cache in solid state drives. In Proceedings of the 26th IEEE Symposium on Mass Storage Systems and Technologies (MSST). 1--12.
[50]
Shimpi, A. L. 2009. Intel x25-m g2: Dissected and performance preview. http://www.anandtech.com/storage/showdoc.aspx?i=3607.
[51]
SiliconSystems. 2005. Increasing flash solid state disk reliability. Tech. rep.
[52]
SimpleScalar LLC. 2009. The simplescalar tool set. http://www.simplescalar.com/.
[53]
Soundararajan, G., Prabhakaran, V., Balakrishnan, M., and Wobber, T. 2010. Extending SSD lifetimes with disk-based write caches. In Proceedings of the 8th USENIX Conference on File and Storage Technologies (FAST'10). USENIX.
[54]
Storage Performance Council. 2010. SPC trace file format specification. http://traces.cs.umass.edu/index. php/Storage/Storage.
[55]
Sun, G., Joo, Y., Chen, Y., Niu, D., Xie, Y., Chen, Y., and Li, H. 2010. A hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. In Proceedings of the 16th IEEE International Symposium on High-Performance Computer Architecture (HPCA-16). IEEE, 141--153.
[56]
Toshiba. 2010. http://www.toshiba.com/taec/news/press-releases/2006/memy-06-337.jsp.
[57]
UMASS. 2007. Umass trace repository. http://traces.cs.umass.edu/index.php/Storage/Storage.
[58]
Wang, Y., Shu, J., Zhang, G., Xue, W., and Zheng, W. 2010. SOPA: Selecting the optimal caching policy adaptively. ACM Trans. Storage 6, 2, 1--18.
[59]
Western Digital. December 2008. WD VelociRaptor SATA hard drives. http://www.wdc.com/en/library/sata/2879-701282.pdf.
[60]
Wu, C.-H. and Kuo, T.-W. 2006. An adaptive two-level management for the flash translation layer in embedded systems. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD'06). ACM, New York, 601--606.
[61]
Zhou, Y., Chen, Z., and Li, K. 2004. Second-level buffer cache management. IEEE Trans. Parallel Distrib. Syst. 15, 6, 505--519.
[62]
Zhou, Y., Philbin, J., and Li, K. 2001. The multi-queue replacement algorithm for second level buffer caches. In Proceedings of the USENIX Annual Technical Conference (General Track). USENIX Association, Berkeley, CA, 91--104.

Cited By

View all
  • (2024)Page Type-Aware Full-Sequence Program Scheduling via Reinforcement Learning in High Density SSDsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344471843:11(3696-3707)Online publication date: 1-Nov-2024
  • (2024)Minato: A Read-Disturb-Aware Dynamic Buffer Management Scheme for NAND Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.336410943:7(1930-1943)Online publication date: 9-Feb-2024
  • (2023)Visibility Graph-based Cache Management for DRAM Buffer Inside Solid-state DrivesACM Transactions on Storage10.1145/358657619:3(1-21)Online publication date: 19-Jun-2023
  • Show More Cited By

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Transactions on Storage
ACM Transactions on Storage  Volume 8, Issue 1
February 2012
92 pages
ISSN:1553-3077
EISSN:1553-3093
DOI:10.1145/2093139
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 24 February 2012
Accepted: 01 June 2011
Revised: 01 May 2011
Received: 01 November 2010
Published in TOS Volume 8, Issue 1

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. NAND flash memory
  2. SSD
  3. flash-aware cache
  4. write buffer

Qualifiers

  • Research-article
  • Research
  • Refereed

Funding Sources

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)35
  • Downloads (Last 6 weeks)1
Reflects downloads up to 13 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2024)Page Type-Aware Full-Sequence Program Scheduling via Reinforcement Learning in High Density SSDsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.344471843:11(3696-3707)Online publication date: 1-Nov-2024
  • (2024)Minato: A Read-Disturb-Aware Dynamic Buffer Management Scheme for NAND Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.336410943:7(1930-1943)Online publication date: 9-Feb-2024
  • (2023)Visibility Graph-based Cache Management for DRAM Buffer Inside Solid-state DrivesACM Transactions on Storage10.1145/358657619:3(1-21)Online publication date: 19-Jun-2023
  • (2023)Fast Online Reconstruction for SSD-Based RAID-5 Storage SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.334803343:6(1886-1899)Online publication date: 28-Dec-2023
  • (2023)Adaptive Management With Request Granularity for DRAM Cache Inside nand-Based SSDsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.322929342:8(2475-2487)Online publication date: 1-Aug-2023
  • (2022)Unifying temporal and spatial locality for cache management inside SSDsProceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe10.5555/3539845.3540054(891-896)Online publication date: 14-Mar-2022
  • (2022)Unifying Temporal and Spatial Locality for Cache Management inside SSDs2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774532(891-896)Online publication date: 14-Mar-2022
  • (2022)Improving Fairness for SSD Devices through DRAM Over-Provisioning Cache ManagementIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2022.314329533:10(2444-2454)Online publication date: 1-Oct-2022
  • (2020)Optimizing synchronization mechanism for block-based file systems using persistent memoryFuture Generation Computer Systems10.1016/j.future.2020.04.024111(288-299)Online publication date: Oct-2020
  • (2019)Transparent Throughput Elasticity for Modern Cloud StorageApplying Integration Techniques and Methods in Distributed Systems and Technologies10.4018/978-1-5225-8295-3.ch007(156-191)Online publication date: 2019
  • Show More Cited By

View Options

Login options

Full Access

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media