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Area-efficient fault detection during self-recovering microarchitecture synthesis

Authors:

Ramesh Karri,

Alex OrailoğluAuthors Info & Claims

DAC '94: Proceedings of the 31st annual Design Automation Conference

Pages 552 - 556

https://doi.org/10.1145/196244.196532

Published: 06 June 1994 Publication History

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References

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R. Karri and A. Orailo~lu. High-Level Synthesis of Fault-Tolerant ASICs. In Proceedings of IEEE International Symposium on Circuits and Systems, May 1992.

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Alex Orailo~lu and Ramesh Karri. Coactive Scheduling and Checkpoint Determination during the High Level Synthesis of Self Recovering Microarchitectures. IEEE Transactions on VLSI Systems, 1994.

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Cited By

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Ozev SOrailoglu A(2004)Design of concurrent test hardware for linear analog circuits with constrained hardware overheadIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2004.82759712:7(756-765)Online publication date: 1-Jul-2004
https://dl.acm.org/doi/10.1109/TVLSI.2004.827597
Zhao WPapachristou C(1996)An evolution programming approach on multiple behaviors for the design of application specific programmable processorsProceedings of the 1996 European conference on Design and Test10.5555/787259.787533Online publication date: 11-Mar-1996
https://dl.acm.org/doi/10.5555/787259.787533
Wei Zhao Papachristou C(1996)An evolution programming approach on multiple behaviors for the design of application specific programmable processorsProceedings ED&TC European Design and Test Conference10.1109/EDTC.1996.494140(144-150)Online publication date: 1996
https://doi.org/10.1109/EDTC.1996.494140
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Index Terms

Area-efficient fault detection during self-recovering microarchitecture synthesis
1. Hardware
  1. Very large scale integration design
2. Theory of computation
  1. Design and analysis of algorithms
    1. Approximation algorithms analysis
      1. Scheduling algorithms
    2. Online algorithms
      1. Online learning algorithms
        Scheduling algorithms
  2. Theory and algorithms for application domains
    1. Machine learning theory
      1. Reinforcement learning
        Sequential decision making

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Information

Published In

DAC '94: Proceedings of the 31st annual Design Automation Conference

June 1994

739 pages

ISBN:0897916530

DOI:10.1145/196244

Chairman:
Michael Lorenzetti
Mentor Graphics Corp., Wilsonville, OR

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 June 1994

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DAC94

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SIGDA
IEEE-CAS

DAC94: The 31st ACM/IEEE-CAS/EDAC Design Automation Conference

June 6 - 10, 1994

California, San Diego, USA

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DAC '94 Paper Acceptance Rate 100 of 260 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

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Ozev SOrailoglu A(2004)Design of concurrent test hardware for linear analog circuits with constrained hardware overheadIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2004.82759712:7(756-765)Online publication date: 1-Jul-2004
https://dl.acm.org/doi/10.1109/TVLSI.2004.827597
Zhao WPapachristou C(1996)An evolution programming approach on multiple behaviors for the design of application specific programmable processorsProceedings of the 1996 European conference on Design and Test10.5555/787259.787533Online publication date: 11-Mar-1996
https://dl.acm.org/doi/10.5555/787259.787533
Wei Zhao Papachristou C(1996)An evolution programming approach on multiple behaviors for the design of application specific programmable processorsProceedings ED&TC European Design and Test Conference10.1109/EDTC.1996.494140(144-150)Online publication date: 1996
https://doi.org/10.1109/EDTC.1996.494140
Harris IOrailoglu ALorenzetti M(1994)Microarchitectural synthesis of VLSI designs with high test concurrencyProceedings of the 31st annual Design Automation Conference10.1145/196244.196353(206-211)Online publication date: 6-Jun-1994
https://dl.acm.org/doi/10.1145/196244.196353
Hogstedt KOrailoglu A(1994)Integrating binding constraints in the synthesis of area-efficient self-recovering microarchitecturesProceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors10.1109/ICCD.1994.331918(331-334)Online publication date: 1994
https://doi.org/10.1109/ICCD.1994.331918
Harris IOrailoglu A(1994)SYNCBIST: SYNthesis for concurrent built-in self-testabilityProceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors10.1109/ICCD.1994.331864(101-104)Online publication date: 1994
https://doi.org/10.1109/ICCD.1994.331864

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Exploiting microarchitecture insights for efficient fault tolerance

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Execution cache-based microarchitecture power-efficient superscalar processors