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A modular partitioning approach for asynchronous circuit synthesis

Authors:

Ruchir Puri,

Jun GuAuthors Info & Claims

DAC '94: Proceedings of the 31st annual Design Automation Conference

Pages 63 - 69

https://doi.org/10.1145/196244.196278

Published: 06 June 1994 Publication History

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Cited By

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Carmona JColom JCortadella JGarcia-Valles F(2006)Synthesis of asynchronous controllers using integer linear programmingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85951625:9(1637-1651)Online publication date: 1-Sep-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.859516
Gu JPuri R(2006)Asynchronous circuit synthesis with Boolean satisfiabilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.40249614:8(961-973)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.402496
Puri R(1999)Asynchronous Logic DesignWiley Encyclopedia of Electrical and Electronics Engineering10.1002/047134608X.W7604Online publication date: 27-Dec-1999
https://doi.org/10.1002/047134608X.W7604
Show More Cited By

Index Terms

A modular partitioning approach for asynchronous circuit synthesis

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A Reconvergence-Based Circuit Partitioning Technique for Combinational and Sequential Logic Synthesis

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Published In

DAC '94: Proceedings of the 31st annual Design Automation Conference

June 1994

739 pages

ISBN:0897916530

DOI:10.1145/196244

Chairman:
Michael Lorenzetti
Mentor Graphics Corp., Wilsonville, OR

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 June 1994

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DAC94: The 31st ACM/IEEE-CAS/EDAC Design Automation Conference

June 6 - 10, 1994

California, San Diego, USA

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DAC '94 Paper Acceptance Rate 100 of 260 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Carmona JColom JCortadella JGarcia-Valles F(2006)Synthesis of asynchronous controllers using integer linear programmingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2005.85951625:9(1637-1651)Online publication date: 1-Sep-2006
https://dl.acm.org/doi/10.1109/TCAD.2005.859516
Gu JPuri R(2006)Asynchronous circuit synthesis with Boolean satisfiabilityIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.40249614:8(961-973)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.402496
Puri R(1999)Asynchronous Logic DesignWiley Encyclopedia of Electrical and Electronics Engineering10.1002/047134608X.W7604Online publication date: 27-Dec-1999
https://doi.org/10.1002/047134608X.W7604
Nagalla R(1998)A new lock based state coding methodology for signal transition graphsISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)10.1109/ISCAS.1998.705241(179-182)Online publication date: 1998
https://doi.org/10.1109/ISCAS.1998.705241
Nagalla RHellestrand G(1997)A Visual Approach for Asynchronous Circuit SynthesisProceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications10.5555/523974.834900Online publication date: 4-Jan-1997
https://dl.acm.org/doi/10.5555/523974.834900
Nagalla RHellestrand G(1997)A visual approach for asynchronous circuit synthesisProceedings Tenth International Conference on VLSI Design10.1109/ICVD.1997.568099(329-335)Online publication date: 1997
https://doi.org/10.1109/ICVD.1997.568099
Nagalla RHellestrand G(1996)Elimination of Dynamic Hazards from Signal Transition GraphsProceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication10.5555/525699.834714Online publication date: 3-Jan-1996
https://dl.acm.org/doi/10.5555/525699.834714
Kudva PGopalakrishnan GJacobson HPennino TYoffa E(1996)A technique for synthesizing distributed burst-mode circuitsProceedings of the 33rd annual Design Automation Conference10.1145/240518.240532(67-70)Online publication date: 1-Jun-1996
https://dl.acm.org/doi/10.1145/240518.240532
Kudva PGopalakrishnan GJacobson H(1996)A technique for synthesizing distributed burst-mode circuits33rd Design Automation Conference Proceedings, 199610.1109/DAC.1996.545548(67-70)Online publication date: 1996
https://doi.org/10.1109/DAC.1996.545548
Ykman-Couvreur CLin B(1995)Optimised state assignment for asynchronous circuit synthesisProceedings Second Working Conference on Asynchronous Design Methodologies10.1109/WCADM.1995.514649(118-127)Online publication date: 1995
https://doi.org/10.1109/WCADM.1995.514649
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Reconvergence-based circuit partitioning technique for combinational and sequential logic synthesis

Asynchronous data-driven circuit synthesis

A Reconvergence-Based Circuit Partitioning Technique for Combinational and Sequential Logic Synthesis