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Domain decomposition methods for circuit simulation

Authors:

U. Kleis,

O. Wallat,

U. Wever,

Q. ZhengAuthors Info & Claims

ACM SIGSIM Simulation Digest, Volume 24, Issue 1

Pages 183 - 186

https://doi.org/10.1145/195291.182588

Published: 01 July 1994 Publication History

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Abstract

In this paper we discuss the application of domain decomposition methods to circuit simulation. This coarse grain parallelization guarantees a minimum of communication and thus achieves good speedup results on a workstation cluster. Our results show that with a cluster of ten powerful RISC workstations comparable turn around times to a supercomputer can be achieved. Furthermore a workstation cluster offers the possibility to simulate electric circuits with a size of new magnitude. On a cluster of 27 workstations we succeeded in simulating a circuit with 135000 transistors, while we failed to simulate the same circuit on our supercomputer because of a lack of memory.

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Cited By

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Bairamkulov RFriedman EBairamkulov RFriedman E(2022)Circuit analysisGraphs in VLSI10.1007/978-3-031-11047-4_5(149-176)Online publication date: 30-Jun-2022
https://doi.org/10.1007/978-3-031-11047-4_5
Ambalavanar VJerome AGunupudi P(2007)Removing redundancy in interconnect simulation using domain decomposition techniques2007 IEEE Workshop on Signal Propagation on Interconnects10.1109/SPI.2007.4512217(85-88)Online publication date: May-2007
https://doi.org/10.1109/SPI.2007.4512217
Jerome AGunupudi PNakhla M(2007)Efficient Parameterized Nonlinear Simulation of VLSI Circuits using Domain Decomposition Techniques2007 IEEE Electrical Performance of Electronic Packaging10.1109/EPEP.2007.4387198(343-346)Online publication date: Oct-2007
https://doi.org/10.1109/EPEP.2007.4387198
Show More Cited By

Index Terms

Domain decomposition methods for circuit simulation
1. Computing methodologies
  1. Modeling and simulation
    1. Simulation types and techniques
      1. Massively parallel and high-performance simulations
2. Hardware
  1. Hardware validation
    1. Functional verification
      1. Simulation and emulation

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Information & Contributors

Information

Published In

ACM SIGSIM Simulation Digest Volume 24, Issue 1

July 1994

192 pages

ISSN:0163-6103

DOI:10.1145/195291

Editors:
D. K. Arvind
Univ. of Edinburgh, Edinburgh, Scotland, UK
,
Rajive Bagrodia
Univ. of California, Los Angeles
,
Jason Yi-Bing Lin
Bellcore, Morristown, NJ

Issue’s Table of Contents

PADS '94: Proceedings of the eighth workshop on Parallel and distributed simulation
August 1994
196 pages
ISBN:1565550277
DOI:10.1145/182478
Editors:
D. K. Arvind
Univ. of Edinburgh, Scotland, UK
,
Rajive Bagrodia
Univ. of California, Los Angeles
,
Jason Yi-Bing Lin
Bellcore

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 July 1994

Published in SIGSIM Volume 24, Issue 1

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Cited By

View all

Bairamkulov RFriedman EBairamkulov RFriedman E(2022)Circuit analysisGraphs in VLSI10.1007/978-3-031-11047-4_5(149-176)Online publication date: 30-Jun-2022
https://doi.org/10.1007/978-3-031-11047-4_5
Ambalavanar VJerome AGunupudi P(2007)Removing redundancy in interconnect simulation using domain decomposition techniques2007 IEEE Workshop on Signal Propagation on Interconnects10.1109/SPI.2007.4512217(85-88)Online publication date: May-2007
https://doi.org/10.1109/SPI.2007.4512217
Jerome AGunupudi PNakhla M(2007)Efficient Parameterized Nonlinear Simulation of VLSI Circuits using Domain Decomposition Techniques2007 IEEE Electrical Performance of Electronic Packaging10.1109/EPEP.2007.4387198(343-346)Online publication date: Oct-2007
https://doi.org/10.1109/EPEP.2007.4387198
GrÄb RGünther MWever UZheng Q(2005)Optimization of parallel multilevel-Newton algorithms on workstation clustersEuro-Par'96 Parallel Processing10.1007/BFb0024689(91-96)Online publication date: 10-Jun-2005
https://doi.org/10.1007/BFb0024689
Le TRejeb J(2004)Performance of parallel logic event simulation on PC-cluster7th International Symposium on Parallel Architectures, Algorithms and Networks, 2004. Proceedings.10.1109/ISPAN.2004.1300518(434-438)Online publication date: 2004
https://doi.org/10.1109/ISPAN.2004.1300518
Frohlich NRiess BWever UQinghua Zheng (1998)A new approach for parallel simulation of VLSI circuits on a transistor levelIEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications10.1109/81.67846845:6(601-613)Online publication date: Jun-1998
https://doi.org/10.1109/81.678468
Wever UZheng Q(1996)Parallel transient analysis for circuit simulationProceedings of HICSS-29: 29th Hawaii International Conference on System Sciences10.1109/HICSS.1996.495492(442-447 vol.1)Online publication date: 1996
https://doi.org/10.1109/HICSS.1996.495492

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Abstract

References

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