Nothing Special   »   [go: up one dir, main page]

skip to main content
article
Free access

Cost/performance of a parallel computer simulator

Published: 01 July 1994 Publication History

Abstract

This paper examines the cost/performance of simulating a hypothetical target parallel computer using a commercial host parallel computer. We address the question of whether parallel simulation is simply faster than sequential simulation, or if it is also more cost-effective. To answer this, we develop a performance model of the Wisconsin Wind Tunnel (WWT), a system that simulates cache-coherent shared-memory machines on a message-passing Thinking Machines CM-5. The performance model uses Kruskal and Weiss's fork-join model to account for the effect of event processing time variability on WWT's conservative fixed-window simulation algorithm. A generalization of Thiebaut and Stone's footprint model accurately predicts the effect of cache interference on the CM-5. The model is calibrated using parameters extracted from a fully-parallel simulation (p=N), and validated by measuring the speedup as the number of processors (p) ranges from one to the number of target nodes (N. Together with simple cost models, the performance model indicates that for target system sizes of 32 nodes and larger, parallel simulation is more cost-effective than sequential simulation. The key intuition behind this result is that large simulations require large memories, which dominate the cost of a uniprocessor; parallel computers allow multiple processors to simultaneously access this large memory.

References

[1]
Rassul Ayani. A Parallel Simulation Scheme Based on the Distance Between Objects. In Proceedings of the SCS Mult~conference on Distmbuted Simulation, pages 113-118, March 1989.
[2]
David Bailey, John Barton, Thomas Lasinski, and Horst Simon. The NAS Parallel Benchmarks. Technical Report RNR-91-002 Revision 2, Ames Research Center, August 1991.
[3]
Bob Boothe. Fast Accurate Simulation of Large Shared Memory Multiprocessors. Technical Report CSD 92/682, Computer Science Division (EECS), University of California at Berkeley, January t992.
[4]
Eric A. Brewer, Chrysanthos N Dellarocas, Adrian CoIbrook, and William Weihl. PROTEUS: A High-Performance Parallel- Architecture Simulator. Technical Report MIT/LCS/TR-516, MIT Laboratory for Computer Science, September 1991.
[5]
Robert F. CmeIik and David Keppel. Shade: A Fast Instruction- Set Simulator for Execution Profiling. Technical Report UWCSE 93-06-06, Department of Computer Science, University of Washington, 1993.
[6]
R.C. Covington, S. Madala, V. Mehta, J.R. Jump, and J.B. Sinclair. The Rice Parallel Processing Testbed. In Proceedings of the 1988 A CM SIGMETRICS Conference on Measurement and Modeling of Con~pu~er Sy~tcrr~, pages 4-11, May 1988.
[7]
Helen Davis, Stephen R. Goldschmidt, and John Hennessy. Multiprocessor Simulation and Tracing Using Tango. In Proceedings of the 1991 International Conference on Parallel Processing (VoI. II Software), pages II99-107, August 1991.
[8]
Richard M. Fujimoto. Parallel Discrete Event Simulation. Communications of the ACM, 33(10):30-53, October 1990.
[9]
Mark D. Hill, James R. Larus, Steven K. Reinhardt, and David A. Wood. Cooperative Shared Memory: Software and Hardware for Scalable Multiprocessors. A CM Transactions on Computer Systems, 11(4):300-318, November 1993. Ealier version appeared in ASPLOS V, Oct. 1992.
[10]
Raj Jain. The Art of Computer Systems Performance Analysts: Technzques for Expemmental Design, Measurement, Simulation, and Modeling. John Wiley & Sons, 1991.
[11]
John L. Hennessy Jaswinder P. Singh and Anoop Gupta. Scaling Parallel Programs for Multiprocessors: Methodology and Examples. IEEE Computer, 26(7):42-50, July 1993.
[12]
C. P. Kruskal and A. Weiss. Allocating Independent Subtasks on Parallel Processors. IEEE Trans. on Software Engzneemng, 11(10):1001-1016, October 1985.
[13]
Charles E. Leiserson, Zahi S. Abuhamdeh, David C. Douglas, Carl g. Feynman, Mahesh N. Ganmukhi, Jeffrey V. Hill, W. Daniel Hillis, Bradley C. KuszmauI, Margaret A. St. Pierre, David S. Wells, Monica C. Wong, Shaw-Wen Yang, and Robert Zak. The Network Architecture of the Connection Machine CM- 5. In Proceedings of the Fifth A CM Symposium on Parallel Algorithms and Architectures (SPAA), July 1992.
[14]
Kai Li and Paul Hudak. Memory Coherence in Shared Virtual Memory Systems. A CM Transactions on Computer Systems, 7(4):321-359, November 1989.
[15]
Jia-Jen Lin. Eflfic~ent Parallel Simulation for Designing Multlprocessor System. PhD thesis, University of Michigan, Ann Arbor, 1992.
[16]
Boris D. Lubachevsky. Efficient Distributed Event-Driven Simulations of Multiple-Loop Networks. Communlcatwns of the ACM, 32(2):111-123, January 1989.
[17]
Jayadev Misra. Distributed-Discrete Event Simulation ACM Computing Surveys, 18(1):39-65, March 1986.
[18]
David Nicot. Conservative Parallel Simulation of Priority Class Queueing Networks. IEEE Transactions on Parallel and D~stributed Systems, 3(3):398-412, May 1992.
[19]
Ed Reidenbach. CHALLENGE Server Perdzod~c Table. Silicon Graphics Computer Systems, October 1993.
[20]
Steven K. Reinhardt, Mark D. Hill, James R. Larus, Alvin R. Lebeck, James C. Lewis, and David A. Wood. The Wisconsin Wind Tunnel: Virtual Prototyping of Parallel Computers. In Proceedings of the 1993 A CM Szgmetmcs Conference on Measurement and Modeling of Computer Systems, pages 48- 60, May 1993.
[21]
Jaswinder Pal Singh, Truman Joe, Anoop Gupta, and John L. Hennessy. An Empirical Comparison of the Kendall Square Research KSR-1 and Stanford DASH Multiprocessor. In Proceed-,ngs of Supercomputzng 93, pages 214-225, November 1993.
[22]
Jaswinder Pal Singh, Wolf-Dietrich Weber, and Anoop Gupta. SPLASH: Stanford Parallel Applications for Shared Memory. Computer Architecture News, 20(1):5-44, March 1992.
[23]
SPEC. SPEC Benchmark Suite Release 1.0, Winter 1990.
[24]
Jeff. S. Steinman. SPEEDES: A Multiple-Synchronization Environment for Parallel Discrete-Event Simulation. International Journal zn Computer Simulation, 2:251-286, 1992.
[25]
D. Thiebaut and H.S. Stone Footprints m the cache. A CM Transactions on Computer Systems, 5(4):305-329, November 1987.
[26]
David A. Wood, Satish Chandra, Babak Falsafi, Mark D. Hill, James R. Larus, Alvin R. Lebeck, James C. Lewis, Shubhendu S. Mukherjee, Subbarao Palacharla, and Steven K. Reinhardt. Mechanisms for Cooperative Shared Memory. In Proceedings of the 20th Annual International Symposium on Computer Architecture, pages 156-168, May 1993.

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM SIGSIM Simulation Digest
ACM SIGSIM Simulation Digest  Volume 24, Issue 1
July 1994
192 pages
ISSN:0163-6103
DOI:10.1145/195291
Issue’s Table of Contents
  • cover image ACM Conferences
    PADS '94: Proceedings of the eighth workshop on Parallel and distributed simulation
    August 1994
    196 pages
    ISBN:1565550277
    DOI:10.1145/182478

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 July 1994
Published in SIGSIM Volume 24, Issue 1

Check for updates

Qualifiers

  • Article

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)80
  • Downloads (Last 6 weeks)13
Reflects downloads up to 16 Dec 2024

Other Metrics

Citations

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media