research-article

Dynamically replicated memory: building reliable systems from nanoscale resistive memories

Authors:

Edmund B. Nightingale,

Thomas MoscibrodaAuthors Info & Claims

ASPLOS XV: Proceedings of the fifteenth International Conference on Architectural support for programming languages and operating systems

Pages 3 - 14

https://doi.org/10.1145/1736020.1736023

Published: 13 March 2010 Publication History

Abstract

DRAM is facing severe scalability challenges in sub-45nm tech- nology nodes due to precise charge placement and sensing hur- dles in deep-submicron geometries. Resistive memories, such as phase-change memory (PCM), already scale well beyond DRAM and are a promising DRAM replacement. Unfortunately, PCM is write-limited, and current approaches to managing writes must de- commission pages of PCM when the first bit fails.

This paper presents dynamically replicated memory (DRM), the first hardware and operating system interface designed for PCM that allows continued operation through graceful degradation when hard faults occur. DRM reuses memory pages that con- tain hard faults by dynamically forming pairs of complementary pages that act as a single page of storage. No changes are required to the processor cores, the cache hierarchy, or the operating sys- tem's page tables. By changing the memory controller, the TLBs, and the operating system to be DRM-aware, we can improve the lifetime of PCM by up to 40x over conventional error-detection techniques.

References

[1]

Y. Azar, A. Broder, A. R. Karlin, and E. Upfal. Balanced allocations. In Symposium on Theory of Computing, May 1994.

Digital Library

[2]

J. Condit, E. Nightingale, C. Frost, E. Ipek, D. Burger, B. Lee, and D. Coetzee. Better I/O through byte-addressable, persistent memory. In International Sympoisum on Operating System Principles, October 2009.

Digital Library

[3]

E. Doller. Phase change memory, September 2009. http://www.pdl. cmu.edu/SDI/2009/slides/Numonyx.pdf.

[4]

M. Dyer, A. Frieze, and B. Pittel. The average performance of the greedy matching algorithm. Annals of Applied Probability, 3(2), 1993.

[5]

J. Edmonds. Path, trees and flowers. Can. J. Math, 17, 1965.

[6]

S. Eilert. PCM fault models, November 2009. Private communication with Sean Eilert, Director of Architecture Pathfinding at Numonyx.

[7]

B. Gleixner, F. Pellizzer, and R. Bez. Reliability characterization of phase change memory. In European Phase Change and Ovonics Symposium, September 2009.

[8]

International technology roadmap for semiconductors. Process integration, devices, and structures, 2009.

[9]

C. Kim, D. Kang, T.-Y. Lee, K. H. P. Kim, Y.-S. Kang, J. Lee, S.-W. Nam, K.-B. Kim, and Y. Khang. Direct evidence of phase separation in Ge2Sb2Te5 in phase change memory devices. Applied Physics Letters, 94(10):5--5, May 2009.

[10]

K. Kim and S. J. Ahn. Reliability investigations for manufacturable high density pram. In IEEE International Reliability Physics Symposium, April 2005.

[11]

B. Lee, E. Ipek, O. Mutlu, and D. Burger. Architecting phase-change memory as a scalable dram alternative. In International Symposium on Computer Architecture, June 2009.

Digital Library

[12]

S. Micali and V. V. Vazirani. An O(√|V ||E|) algorithm for finding maximum matching in general graphs. In FOCS, 1980.

Digital Library

[13]

R. Micheloni, A. Marelli, and R. Ravasio. In Error Correction Codes for Non-Volatile Memories, 2008.

Digital Library

[14]

Micron. 512Mb DDR2 SDRAM Component Data Sheet: MT47H128 M4B6--25, March 2006. http://download.micron.com/pdf/datasheets/ dram/ddr2/512MbDDR2.pdf.

[15]

M. D. Mitzenmacher. The power of two choices in randomized load balancing. Doctoral Dissertaion, Graduate Division of the University of California at Berkeley, 1996.

Digital Library

[16]

T. N. Mudge, G. S. Dasika, and D. A. Roberts. Storage of data in data stores having some faulty storage locations, March 2008. United States Patent Application 20080077824.

[17]

Numonyx. The basics of PCM technology, September 2008. http:// www.numonyx.com/Documents/WhitePapers.

[18]

Numonyx. Phase change memory: A new memory technology to enable new memory usage models, September 2009.http://www. numonyx.com/Documents/WhitePapers.

[19]

A. Pirovano, A. Radaelli, F. Pellizzer, F. Ottogalli, M. Tosi, D. Ielmini, A. L. Lacaita, and R. Bez. Reliability study of phase-change non-volatile memories. IEEE Transactions on Device and Materials Reliability, 4(3):422--427, September 2004.

[20]

M. K. Qureshi, M. Fraceschini, V. Srinivasan, L. Lastras, B. Abali, and J. Karidis. Enhancing lifetime and security of phase change memories via start-gap wear leveling. In International Symposium on Microarchitecture, November 2009.

Digital Library

[21]

M. K. Qureshi, V. Srinivasan, and J. A. Rivers. Scalable high performance main memory system using phase-change memory technology. In International Symposium on Computer Architecture, June 2009.

Digital Library

[22]

S. Raoux, D. M. Ritchiea, K. Thompsona, D. M. Ritchiea, K. Thompsona, D. M. Ritchiea, and K. Thompson. Phase-change random access memory: A scalable technology. IBM Journal of Research and Development, 52(7):5--5, July 2008.

Digital Library

[23]

J. Renau, B. Fraguela, J. Tuck, W. Liu, M. Prvulovic, L. Ceze, S. Sarangi, P. Sack, K. Strauss, and P. Montesinos SESC simulator, January 2005. http://sesc.sourceforge.net.

[24]

D. Roberts, N. S. Kim, and T. Mudge. On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology. In Euromicro Conference on Digital System Design, August 2007.

Digital Library

[25]

D. Roberts, N. S. Kim, and T. Mudge. On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology. Elsevier Microprocessors and Microsystems, 2008.

Digital Library

[26]

J. Rodgers, J. Maimon, T. Storey, D. Lee, M. Graziano, L. Rockett, and K. Hunt. A 4-mb non-volatile chalcogenide random access memory designed for space applications: Project status update. In IEEE Non-Volatile Memory Technology Symposium, November 2008.

[27]

Samsung. Bad-block management, September 2009. http://www. samsung.com/global/business/semiconductor/products/flash/downloads /xsr v15 badblockmgmt application note.pdf

[28]

D. Tarjan, S. Thoziyoor, and N. P. Jouppi. Cacti 4.0. Technical report, HP Labs, 2006.

[29]

X. Wu, J. Li, L. Zhang, E. Speight, R. Rajamony, and Y. Xie. Hybrid cache architecture with disparate memory technologies. In International Symposium on Computer Architecture, June 2009.

Digital Library

[30]

W. Zhang and T. Li. Characterizing and mitigating the impact of process variations on phase change based memory systems. In International Symposium on Microarchitecture, September 2009.

Digital Library

[31]

W. Zhang and T. Li. Exploring phase change memory and 3d die-stacking for power/thermal friendly, fast and durable memory architectures. In International Conference on Parallel Architectures and Compilation Techniques, September 2009.

Digital Library

[32]

H. Zhou and Z.-C. Ou-Yang. Maximum Matching on Random Graphs. Europhsics Letters -- Preprint, 2003.

[33]

P. Zhouand, B. Zhao, J. Yang, and Y. Zhang. A durable and energy efficient main memory using phase change memory technology. In International Symposium on Computer Architecture, June 2009.

Digital Library

Cited By

Ye CChen MJiang QWang C(2024)Hercules: Enabling Atomic Durability for Persistent Memory with Transient Persistence DomainACM Transactions on Embedded Computing Systems10.1145/360747323:6(1-34)Online publication date: 11-Sep-2024
https://dl.acm.org/doi/10.1145/3607473
Lanka SKonjeti PPinto C(2024)A Review: Complete Analysis of the Cache Architecture for Better Performance2024 Second International Conference on Inventive Computing and Informatics (ICICI)10.1109/ICICI62254.2024.00129(768-771)Online publication date: 11-Jun-2024
https://doi.org/10.1109/ICICI62254.2024.00129
Urquijo GVoelckers KMeyer ABellinger CAsadinia M(2023)SW-PCM: Graceful Degradation Support in PCM Main Memories by Using Swaption MechanismProceedings of the Future Technologies Conference (FTC) 2023, Volume 310.1007/978-3-031-47457-6_34(514-531)Online publication date: 9-Nov-2023
https://doi.org/10.1007/978-3-031-47457-6_34
Show More Cited By

Index Terms

Dynamically replicated memory: building reliable systems from nanoscale resistive memories
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Phase-Change Memory (PCM) technology has received substantial attention recently. Because PCM is byte-addressable and exhibits access times in the nanosecond range, it can be used in main memory designs. In fact, PCM has higher density and lower idle ...
Dynamically replicated memory: building reliable systems from nanoscale resistive memories
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DRAM is facing severe scalability challenges in sub-45nm tech- nology nodes due to precise charge placement and sensing hur- dles in deep-submicron geometries. Resistive memories, such as phase-change memory (PCM), already scale well beyond DRAM and are ...
Dynamically replicated memory: building reliable systems from nanoscale resistive memories
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DRAM is facing severe scalability challenges in sub-45nm tech- nology nodes due to precise charge placement and sensing hur- dles in deep-submicron geometries. Resistive memories, such as phase-change memory (PCM), already scale well beyond DRAM and are ...

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cover image ACM Conferences

ASPLOS XV: Proceedings of the fifteenth International Conference on Architectural support for programming languages and operating systems

March 2010

422 pages

ISBN:9781605588391

DOI:10.1145/1736020

General Chair:
James C. Hoe
Carnegie Mellon University, USA
,
Program Chair:
Vikram S. Adve
University of Illinois at Urbana-Champaign, USA

ACM SIGARCH Computer Architecture News Volume 38, Issue 1
ASPLOS '10
March 2010
399 pages
ISSN:0163-5964
DOI:10.1145/1735970
Issue’s Table of Contents
ACM SIGPLAN Notices Volume 45, Issue 3
ASPLOS '10
March 2010
399 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/1735971
Issue’s Table of Contents

Copyright © 2010 ACM.

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Published: 13 March 2010

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ASPLOS '10: Architectural Support for Programming Languages and Operating Systems

March 13 - 17, 2010

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ASPLOS XV Paper Acceptance Rate 32 of 181 submissions, 18%;

Overall Acceptance Rate 535 of 2,713 submissions, 20%

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Cited By

Ye CChen MJiang QWang C(2024)Hercules: Enabling Atomic Durability for Persistent Memory with Transient Persistence DomainACM Transactions on Embedded Computing Systems10.1145/360747323:6(1-34)Online publication date: 11-Sep-2024
https://dl.acm.org/doi/10.1145/3607473
Lanka SKonjeti PPinto C(2024)A Review: Complete Analysis of the Cache Architecture for Better Performance2024 Second International Conference on Inventive Computing and Informatics (ICICI)10.1109/ICICI62254.2024.00129(768-771)Online publication date: 11-Jun-2024
https://doi.org/10.1109/ICICI62254.2024.00129
Urquijo GVoelckers KMeyer ABellinger CAsadinia M(2023)SW-PCM: Graceful Degradation Support in PCM Main Memories by Using Swaption MechanismProceedings of the Future Technologies Conference (FTC) 2023, Volume 310.1007/978-3-031-47457-6_34(514-531)Online publication date: 9-Nov-2023
https://doi.org/10.1007/978-3-031-47457-6_34
Patel Mde Oliveira GMutlu O(2021)HARP: Practically and Effectively Identifying Uncorrectable Errors in Memory Chips That Use On-Die Error-Correcting CodesMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480061(623-640)Online publication date: 18-Oct-2021
https://dl.acm.org/doi/10.1145/3466752.3480061
Patil ANagarajan VBalasubramonian ROswald NMartínez JDuato JJohn L(2021)DvéProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00048(526-539)Online publication date: 14-Jun-2021
https://dl.acm.org/doi/10.1109/ISCA52012.2021.00048
Chen SChen TChang YWei HShih W(2020)A Partial Page Cache Strategy for NVRAM-Based Storage DevicesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.288704539:2(373-386)Online publication date: Feb-2020
https://doi.org/10.1109/TCAD.2018.2887045
Yavits LOrosa LMahar SFerreira JErez MGinosar RMutlu O(2020)WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders2020 IEEE 38th International Conference on Computer Design (ICCD)10.1109/ICCD50377.2020.00044(187-196)Online publication date: Oct-2020
https://doi.org/10.1109/ICCD50377.2020.00044
Gogte VWang WDiestelhorst SKolli AChen PNarayanasamy SWenisch TMerchant AWeatherspoon H(2019)Software wear management for persistent memoriesProceedings of the 17th USENIX Conference on File and Storage Technologies10.5555/3323298.3323303(45-63)Online publication date: 25-Feb-2019
https://dl.acm.org/doi/10.5555/3323298.3323303
Rashidi SJalili MSarbazi-Azad H(2019)A Survey on PCM Lifetime Enhancement SchemesACM Computing Surveys10.1145/333225752:4(1-38)Online publication date: 30-Aug-2019
https://dl.acm.org/doi/10.1145/3332257
Xu JFeng DHua YHuang FZhou WTong WLiu J(2019)An Efficient Spare-Line Replacement Scheme to Enhance NVM SecurityProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317767(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317767
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