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Warp architecture and implementation

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M. S. LamAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 14, Issue 2

Pages 346 - 356

https://doi.org/10.1145/17356.17397

Published: 01 May 1986 Publication History

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Abstract

This paper describes the scan line array processor (SLAP), a new architecture designed for high-performance yet low-cost image computation. A SLAP is a SIMD linear array of processors, and hence is easy to build and scales well with VLSI technology; yet appropriate special features and programming techniques make it efficient for a surprisingly wide variety of low and medium level computer vision tasks. We describe the basic SLAP concept and some of its variants, discuss a particular planned implementation, and indicate its performance on computer vision and other applications.

References

[1]

Fisher, A.L., Kung, H.T., Monier, L.M. and Dohi. Y. "The Architecture of a Programmable Systolic Chip". Journal of VLSI and Computer Systems 1, 2 (1984), 153-169. An earlier version appears in Conference Proceedings of the lOth Annual Symposium on Computer Architecture, Stockholm, Sweden, June 1983, pp. 48-53.

Digital Library

Google Scholar

[2]

Gross, T. and ltm, M. Compilation fora High-performance Systolic Array. Proceedings of the SIGPLAN 86 Symposium on Compiler Construction, ACM SigPlan, June, 1986.

Digital Library

Google Scholar

[3]

Gross, T., Kung, H.T., Lain, M. and Webb, J. Warp as a Machine for Low-level Vision. Proceedings of 1985 IEEE International Conference on Robotics and Automation, March, 1985, pp. 790-800.

Crossref

Google Scholar

[4]

Kung. H.T. "Memory Requirements for Balanced Computer Architectures". Journal nfComplexity 1, 1 (1985), 147-157. (A revised version also appears in Conference Proceedings of the 13th Annual International Symposium on Computer Architecture, June 1986).

Digital Library

Google Scholar

[5]

Kung, H.T. and Lain, M. "Wafer-Scale Integration and Two- Level Pipelined Implementations of Systolic Arrays ". Journal of Paralleland Distributed Computing 1, l (1984), 32-63. A preliminary version appeared in Proceedings of the Conference on Admnced Research in VLSI, MIT, January 1984.

Google Scholar

[6]

Kung, H.T. and Webb, J.A. Global Operations on the CMU Warp Machine. Proceedings of 1985 AIAA Computers in Aerospace V Conference, American Institute of Aeronautics and Astronautics. October, 1985, pp. 209-218.

Crossref

Google Scholar

[7]

Rau, 13. R. and Glaeser, C. D. Some Scheduling Techniques and an Easily Schedulable Horizontal Architecture for High Performance Scientific Computing. Proc. 14th Annual Workshop on Mieroprogramming, Oct., 1981, pp. 183-198.

Digital Library

Google Scholar

[8]

Wallace, R., Matsuzaki, K., Goto, Y., Crisman, J., Webb, J. and Kanade, T. Progress in Robot Read-Following. Proceedings of 1986 IEEE International Conference on Robotics and Automation, April, 1986.

Crossref

Google Scholar

[9]

Woo, B., Jan, L. and Ware, F. A High-Speed 32 Bit IEEE Floating-Point Chip Set for Digital Signal Processing. Proceedings of 1984 IEEE International Conference on Acoustics, Speech and Signal processing, 1984, pp. 16.6.1-16.6.4.

Google Scholar

Cited By

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(2011)BibliographyPractical Parallel Rendering10.1201/b10622-13(337-362)Online publication date: 19-Apr-2011
https://doi.org/10.1201/b10622-13
Chien SChen L(2011)Reconfigurable Morphological Image Processing Accelerator for Video Object SegmentationJournal of Signal Processing Systems10.1007/s11265-008-0311-662:1(77-96)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1007/s11265-008-0311-6
Gribomont PDongen V(2005)Generic systolic arrays: A methodology for systolic designTAPSOFT'93: Theory and Practice of Software Development10.1007/3-540-56610-4_102(746-761)Online publication date: 28-May-2005
https://doi.org/10.1007/3-540-56610-4_102
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Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 14, Issue 2

Special Issue: Proceedings of the 13th annual international symposium on Computer architecture (ISCA '86)

May 1986

429 pages

ISSN:0163-5964

DOI:10.1145/17356

Editor:
Hideo Aiso

Issue’s Table of Contents

ISCA '86: Proceedings of the 13th annual international symposium on Computer architecture
June 1986
454 pages
ISBN:081860719X
Chairman:
Hideo Aiso

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1986

Published in SIGARCH Volume 14, Issue 2

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(2011)BibliographyPractical Parallel Rendering10.1201/b10622-13(337-362)Online publication date: 19-Apr-2011
https://doi.org/10.1201/b10622-13
Chien SChen L(2011)Reconfigurable Morphological Image Processing Accelerator for Video Object SegmentationJournal of Signal Processing Systems10.1007/s11265-008-0311-662:1(77-96)Online publication date: 1-Jan-2011
https://dl.acm.org/doi/10.1007/s11265-008-0311-6
Gribomont PDongen V(2005)Generic systolic arrays: A methodology for systolic designTAPSOFT'93: Theory and Practice of Software Development10.1007/3-540-56610-4_102(746-761)Online publication date: 28-May-2005
https://doi.org/10.1007/3-540-56610-4_102
Gross TSussman A(2005)Mapping a single-assignment language onto the warp systolic arrayFunctional Programming Languages and Computer Architecture10.1007/3-540-18317-5_19(347-363)Online publication date: 27-May-2005
https://doi.org/10.1007/3-540-18317-5_19
Treleaven PRefenes ALees KMcCabe S(2005)Computer architectures for artificial intelligenceFuture Parallel Computers10.1007/3-540-18203-9_15(416-492)Online publication date: 28-May-2005
https://doi.org/10.1007/3-540-18203-9_15
Staunton R(1999)Hexagonal Sampling in Image Processing10.1016/S1076-5670(08)70188-5(231-307)Online publication date: 1999
https://doi.org/10.1016/S1076-5670(08)70188-5
Aiken ANicolau ANovack S(1995)Resource-Constrained Software PipeliningIEEE Transactions on Parallel and Distributed Systems10.1109/71.4761676:12(1248-1270)Online publication date: 1-Dec-1995
https://dl.acm.org/doi/10.1109/71.476167
Peterson CSutton JWiley P(1991)iWarpIEEE Micro10.1109/40.8756811:3(26-29, 81-87)Online publication date: 1-May-1991
https://dl.acm.org/doi/10.1109/40.87568
Alnuweiri HPrasanna V(1991)Optimal geometric algorithms for digitized images on fixed-size linear arrays and scan-line arraysDistributed Computing10.1007/BF022597475:2(55-65)Online publication date: 1-Sep-1991
https://dl.acm.org/doi/10.1007/BF02259747
Alnuweiri HPrasanna Kumar V(1991)Processor-time optimal parallel algorithms for digitized images on mesh-connected processor arraysAlgorithmica10.1007/BF017590686:1-6(698-733)Online publication date: 1-Jun-1991
https://dl.acm.org/doi/10.1007/BF01759068
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Warp architecture and implementation

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