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Warp architecture and implementation

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M. S. LamAuthors Info & Claims

ISCA '86: Proceedings of the 13th annual international symposium on Computer architecture

Pages 346 - 356

Published: 01 May 1986 Publication History

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Abstract

This paper describes the scan line array processor (SLAP), a new architecture designed for high-performance yet low-cost image computation. A SLAP is a SIMD linear array of processors, and hence is easy to build and scales well with VLSI technology; yet appropriate special features and programming techniques make it efficient for a surprisingly wide variety of low and medium level computer vision tasks. We describe the basic SLAP concept and some of its variants, discuss a particular planned implementation, and indicate its performance on computer vision and other applications.

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Cited By

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Hoffmann HDevadas SAgarwal A(2010)A pattern for efficient parallel computation on multicore processors with scalar operand networksProceedings of the 2010 Workshop on Parallel Programming Patterns10.1145/1953611.1953614(1-9)Online publication date: 30-Mar-2010
https://dl.acm.org/doi/10.1145/1953611.1953614
Aiken ANicolau ANovack S(1995)Resource-Constrained Software PipeliningIEEE Transactions on Parallel and Distributed Systems10.1109/71.4761676:12(1248-1270)Online publication date: 1-Dec-1995
https://dl.acm.org/doi/10.1109/71.476167
Ward SAbdalla KDujari RFetterman MHonoré FJenez RLaffont PMackenzie KMetcalf CMinsky MNguyen JPezaris JPratt GTessier RMuraoka Y(1993)The NuMeshProceedings of the 7th international conference on Supercomputing10.1145/165939.165973(230-239)Online publication date: 1-Aug-1993
https://dl.acm.org/doi/10.1145/165939.165973
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Information

Published In

ISCA '86: Proceedings of the 13th annual international symposium on Computer architecture

June 1986

454 pages

ISBN:081860719X

Chairman:
Hideo Aiso

ACM SIGARCH Computer Architecture News Volume 14, Issue 2
Special Issue: Proceedings of the 13th annual international symposium on Computer architecture (ISCA '86)
May 1986
429 pages
ISSN:0163-5964
DOI:10.1145/17356
Editor:
Hideo Aiso
Issue’s Table of Contents

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 May 1986

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Hoffmann HDevadas SAgarwal A(2010)A pattern for efficient parallel computation on multicore processors with scalar operand networksProceedings of the 2010 Workshop on Parallel Programming Patterns10.1145/1953611.1953614(1-9)Online publication date: 30-Mar-2010
https://dl.acm.org/doi/10.1145/1953611.1953614
Aiken ANicolau ANovack S(1995)Resource-Constrained Software PipeliningIEEE Transactions on Parallel and Distributed Systems10.1109/71.4761676:12(1248-1270)Online publication date: 1-Dec-1995
https://dl.acm.org/doi/10.1109/71.476167
Ward SAbdalla KDujari RFetterman MHonoré FJenez RLaffont PMackenzie KMetcalf CMinsky MNguyen JPezaris JPratt GTessier RMuraoka Y(1993)The NuMeshProceedings of the 7th international conference on Supercomputing10.1145/165939.165973(230-239)Online publication date: 1-Aug-1993
https://dl.acm.org/doi/10.1145/165939.165973
Alnuweiri HPrasanna V(1991)Optimal geometric algorithms for digitized images on fixed-size linear arrays and scan-line arraysDistributed Computing10.1007/BF022597475:2(55-65)Online publication date: 1-Sep-1991
https://dl.acm.org/doi/10.1007/BF02259747
Su BWang JTang ZZhao WWu YPapachristou CAllan V(1990)A software pipelining based VLIW architecture and optimizing compilerProceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture10.5555/255237.255244(17-27)Online publication date: 30-Nov-1990
https://dl.acm.org/doi/10.5555/255237.255244
Majumdar ARaghavendra CBreuer M(1990)Fault Tolerance in Linear Systolic Arrays Using Time RedundancyIEEE Transactions on Computers10.1109/12.4521439:2(269-276)Online publication date: 1-Feb-1990
https://dl.acm.org/doi/10.1109/12.45214
Melhem R(1989)A Systolic Accelerator for the Iterative Solution of Sparse Linear SystemsIEEE Transactions on Computers10.1109/12.4213238:11(1591-1595)Online publication date: 1-Nov-1989
https://dl.acm.org/doi/10.1109/12.42132
Menzilcioglu O(1988)A case study in using two-level control storesACM SIGMICRO Newsletter10.1145/62185.6219319:3(46-48)Online publication date: 1-Sep-1988
https://dl.acm.org/doi/10.1145/62185.62193
Kung H(1988)Warp experience: we can map computations onto a parallel computer efficientlyProceedings of the 2nd international conference on Supercomputing10.1145/55364.55430(668-675)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.1145/55364.55430
Bruegge BGross T(1988)An integrated environment for development and execution of real-time programsProceedings of the 2nd international conference on Supercomputing10.1145/55364.55379(153-163)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.1145/55364.55379
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