research-article

NoC topology synthesis for supporting shutdown of voltage islands in SoCs

Authors:

Ciprian Seiculescu,

Srinivasan Murali,

Giovanni De MicheliAuthors Info & Claims

DAC '09: Proceedings of the 46th Annual Design Automation Conference

Pages 822 - 825

https://doi.org/10.1145/1629911.1630121

Published: 26 July 2009 Publication History

Abstract

In many Systems on Chips (SoCs), the cores are clustered in to voltage islands. When cores in an island are unused, the entire island can be shutdown to reduce the leakage power consumption. However, today, the interconnect architecture is a bottleneck in allowing the shutdown of the islands. In this paper, we present a synthesis approach to obtain customized application-specific Networks on Chips (NoCs) that can support the shutdown of voltage islands. Our results on realistic SoC benchmarks show that the resulting NoC designs only have a negligible overhead in SoC active power consumption (average of 3%) and area (average of 0.5%) to support the shutdown of islands. The shutdown support provided can lead to a significant leakage and hence total power savings.

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Cited By

Kashi SPatooghy ARahmati DFazeli M(2022)A multi-application approach for synthesizing custom network-on-chipsThe Journal of Supercomputing10.1007/s11227-022-04444-078:13(15358-15380)Online publication date: 16-Apr-2022
https://doi.org/10.1007/s11227-022-04444-0
Crespo JSánchez JAlfaro-Cortés FFlich JDuato J(2021)UPR: deadlock-free dynamic network reconfiguration by exploiting channel dependency graph compatibilityThe Journal of Supercomputing10.1007/s11227-021-03791-8Online publication date: 14-Apr-2021
https://doi.org/10.1007/s11227-021-03791-8
Kashi SPatooghy ARahmati DFazeli MKinsy M(2018)Application Specific Networks-on-Chip Synthesis: An Energy Efficient Approach2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2018.00020(52-57)Online publication date: Jul-2018
https://doi.org/10.1109/ISVLSI.2018.00020
Show More Cited By

Index Terms

NoC topology synthesis for supporting shutdown of voltage islands in SoCs
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Buses and high-speed links

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cover image ACM Conferences

DAC '09: Proceedings of the 46th Annual Design Automation Conference

July 2009

994 pages

ISBN:9781605584973

DOI:10.1145/1629911

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems

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Association for Computing Machinery

New York, NY, United States

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Published: 26 July 2009

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DAC '09

Sponsor:

EDAC
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DAC '09: The 46th Annual Design Automation Conference 2009

July 26 - 31, 2009

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Kashi SPatooghy ARahmati DFazeli M(2022)A multi-application approach for synthesizing custom network-on-chipsThe Journal of Supercomputing10.1007/s11227-022-04444-078:13(15358-15380)Online publication date: 16-Apr-2022
https://doi.org/10.1007/s11227-022-04444-0
Crespo JSánchez JAlfaro-Cortés FFlich JDuato J(2021)UPR: deadlock-free dynamic network reconfiguration by exploiting channel dependency graph compatibilityThe Journal of Supercomputing10.1007/s11227-021-03791-8Online publication date: 14-Apr-2021
https://doi.org/10.1007/s11227-021-03791-8
Kashi SPatooghy ARahmati DFazeli MKinsy M(2018)Application Specific Networks-on-Chip Synthesis: An Energy Efficient Approach2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2018.00020(52-57)Online publication date: Jul-2018
https://doi.org/10.1109/ISVLSI.2018.00020
Wang KDong SJiao F(2017)TSF3D: MSV-Driven Power Optimization for Application-Specific 3D Network-on-ChipIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.265098936:7(1089-1102)Online publication date: Jul-2017
https://doi.org/10.1109/TCAD.2017.2650989
Bokhari HParameswaran S(2017)Network-on-Chip DesignHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_16-1(1-29)Online publication date: 20-Apr-2017
https://doi.org/10.1007/978-94-017-7358-4_16-1
Bokhari HParameswaran S(2017)Network-on-Chip DesignHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_16(461-489)Online publication date: 27-Sep-2017
https://doi.org/10.1007/978-94-017-7267-9_16
Wang KDong S(2014)Post-floorplanning power optimization for MSV-driven application specific NoC design2014 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2014.6865305(994-997)Online publication date: Jun-2014
https://doi.org/10.1109/ISCAS.2014.6865305
Sem-Jacobsen FRodrigo SStrano ASkeie TBertozzi DGilabert F(2013)Enabling power efficiency through dynamic rerouting on-chipACM Transactions on Embedded Computing Systems10.1145/2485984.248599912:4(1-23)Online publication date: 3-Jul-2013
https://dl.acm.org/doi/10.1145/2485984.2485999
Kapadia NPasricha S(2013)A co-synthesis methodology for power delivery and data interconnection networks in 3D ICsInternational Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2013.6523593(73-79)Online publication date: Mar-2013
https://doi.org/10.1109/ISQED.2013.6523593
Kan Wang Sheqin Dong (2013)Power optimization for application-specific 3D network-on-chip with multiple supply voltages2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2013.6509622(362-367)Online publication date: Jan-2013
https://doi.org/10.1109/ASPDAC.2013.6509622
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