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A power-effective scan architecture using scan flip-flops clustering and post-generation filling

Published: 10 May 2009 Publication History

Abstract

In this paper, we propose a novel way to save test power, using the DFT based technique as basic method and post-generation filling as complementary. In this architecture, two methods of clustering flip-flops into scan chains are presented. One is clustering scan flip-flops into two parts to save capture power, and the other is clustering scan flip-flops of each part into scan chains to save shift power. By partitioning the scan flip-flops into two parts, the capture operation is cut into two sequential steps, which can effectively reduce the capture power. By partitioning flip-flops with common successors into one chain, we can make sure that, only one or a small part of scan chains are active during the shifting phase. For other scan chains, filling strategy is used as complementary method to further reduce test power. This architecture can effectively reduce the test time too. Experimental results show that average power reduction of 91.81% and average peak power reduction of 49.35% can be achieved, comparing to the ordinary full-scan architecture.

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Cited By

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  • (2014)Path-Dividing Based Scheduling Algorithm for Reducing Energy Consumption of Clustered VLIW ArchitecturesIEEE Transactions on Computers10.1109/TC.2013.13863:10(2526-2539)Online publication date: Oct-2014

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      cover image ACM Conferences
      GLSVLSI '09: Proceedings of the 19th ACM Great Lakes symposium on VLSI
      May 2009
      558 pages
      ISBN:9781605585222
      DOI:10.1145/1531542
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 10 May 2009

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      Author Tags

      1. design for test
      2. low power
      3. scan design
      4. test

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      May 10 - 12, 2009
      MA, Boston Area, USA

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      • (2014)Path-Dividing Based Scheduling Algorithm for Reducing Energy Consumption of Clustered VLIW ArchitecturesIEEE Transactions on Computers10.1109/TC.2013.13863:10(2526-2539)Online publication date: Oct-2014

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