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AutoFix: a hybrid tool for automatic logic rectification

Published: 01 November 2006 Publication History

Abstract

We address the problem of rectifying an erroneous combinational circuit. Based on the symbolic binary decision diagram techniques, we consider the rectification process as a sequence of partial corrections. Each partial correction reduces the size of the input vector set that produces error responses. Compared with the existing approaches, this approach is more general, and thus, suitable for circuits with multiple errors and for the engineering change problem. Also, we derive the necessary and sufficient condition of general single-gate correction to improve the quality of rectification. To handle larger circuits, we develop a hybrid approach that makes use of the information of structural correspondence between specification and implementation. Experiments are performed on a suite of industrial examples as well as the entire set of ISCAS'85 benchmark circuits to demonstrate its effectiveness

Cited By

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  • (2019)Comprehensive Search for ECO Rectification Using Symbolic SamplingProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317790(1-6)Online publication date: 2-Jun-2019
  • (2017)CEGAR-based EF synthesis of Boolean functions with an application to circuit rectification2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2017.7858328(251-256)Online publication date: 16-Jan-2017
  • (2016)Resource-aware functional ECO patch generationProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972050(1036-1041)Online publication date: 14-Mar-2016
  • Show More Cited By

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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Volume 18, Issue 9
November 2006
182 pages

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IEEE Press

Publication History

Published: 01 November 2006

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Cited By

View all
  • (2019)Comprehensive Search for ECO Rectification Using Symbolic SamplingProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317790(1-6)Online publication date: 2-Jun-2019
  • (2017)CEGAR-based EF synthesis of Boolean functions with an application to circuit rectification2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2017.7858328(251-256)Online publication date: 16-Jan-2017
  • (2016)Resource-aware functional ECO patch generationProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972050(1036-1041)Online publication date: 14-Mar-2016
  • (2014)Engineering change orders design using multiple variables linear programming for VLSI designVLSI Design10.1155/2014/6980412014(8-8)Online publication date: 1-Jan-2014
  • (2013)Intuitive ECO synthesis for high performance circuitsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485529(1002-1007)Online publication date: 18-Mar-2013
  • (2012)Multi-patch generation for multi-error logic rectification by interpolation with cofactor reductionProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2493091(1567-1572)Online publication date: 12-Mar-2012
  • (2012)ICCAD-2012 CAD contest in finding the minimal logic difference for functional ECO and benchmark suiteProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429455(342-344)Online publication date: 5-Nov-2012
  • (2011)Match and replaceProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132421(383-388)Online publication date: 7-Nov-2011
  • (2011)Interpolation-based incremental ECO synthesis for multi-error logic rectificationProceedings of the 48th Design Automation Conference10.1145/2024724.2024758(146-151)Online publication date: 5-Jun-2011
  • (2009)Towards automated ECOs in FPGAsProceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1508128.1508131(3-12)Online publication date: 24-Feb-2009
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