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Fast approximation of the transient response of Lossy Transmision Line Trees

Authors:

M. Sriram,

S. M. KangAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 691 - 696

https://doi.org/10.1145/157485.165093

Published: 01 July 1993 Publication History

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Hong JBaek DSon HAhn CKim BPark HSim J(2020)A pattern-dependent injection-locked CDR for clock-embedded signalingMicroelectronics Journal10.1016/j.mejo.2020.10470896(104708)Online publication date: Feb-2020
https://doi.org/10.1016/j.mejo.2020.104708
Sanaullah MChowdhury M(2014)A new real pole delay model for RLC interconnect using second order approximation2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2014.6908396(238-241)Online publication date: Aug-2014
https://doi.org/10.1109/MWSCAS.2014.6908396
Sanaullah MChowdhury M(2014)Analysis of RLC interconnect delay model using second order approximation2014 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2014.6865744(2756-2759)Online publication date: Jun-2014
https://doi.org/10.1109/ISCAS.2014.6865744
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Index Terms

Fast approximation of the transient response of Lossy Transmision Line Trees
1. Hardware
  1. Hardware test
    1. Test-pattern generation and fault simulation
  2. Integrated circuits
    1. Interconnect
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory
      1. Trees
  2. Mathematical analysis
    1. Numerical analysis
      1. Computations on polynomials

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Published In

DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 July 1993

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DAC93

Sponsor:

EDAC
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IEEE-CAS

DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

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Overall Acceptance Rate 299 of 1,119 submissions, 27%

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Cited By

View all

Hong JBaek DSon HAhn CKim BPark HSim J(2020)A pattern-dependent injection-locked CDR for clock-embedded signalingMicroelectronics Journal10.1016/j.mejo.2020.10470896(104708)Online publication date: Feb-2020
https://doi.org/10.1016/j.mejo.2020.104708
Sanaullah MChowdhury M(2014)A new real pole delay model for RLC interconnect using second order approximation2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS.2014.6908396(238-241)Online publication date: Aug-2014
https://doi.org/10.1109/MWSCAS.2014.6908396
Sanaullah MChowdhury M(2014)Analysis of RLC interconnect delay model using second order approximation2014 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2014.6865744(2756-2759)Online publication date: Jun-2014
https://doi.org/10.1109/ISCAS.2014.6865744
Kahng AMuddu S(2006)An analytical delay model for RLC interconnectsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.66423116:12(1507-1514)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.664231
Abbaspour SPedram MImai M(2004)Gate delay calculation considering the crosstalk capacitancesProceedings of the 2004 Asia and South Pacific Design Automation Conference10.5555/1015090.1015318(852-857)Online publication date: 27-Jan-2004
https://dl.acm.org/doi/10.5555/1015090.1015318
Abbaspour SPedram M(2004)Gate delay calculation considering the crosstalk capacitancesASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)10.1109/ASPDAC.2004.1337714(853-858)Online publication date: 2004
https://doi.org/10.1109/ASPDAC.2004.1337714
Qin ZCheng CYasuura H(2003)RCLK-VJ network reduction with Hurwitz polynomial approximationProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119827(283-291)Online publication date: 21-Jan-2003
https://dl.acm.org/doi/10.1145/1119772.1119827
Abbaspour SPedram MYasuura H(2003)Calculating the effective capacitance for the RC interconnect in VDSM technologiesProceedings of the 2003 Asia and South Pacific Design Automation Conference10.1145/1119772.1119781(43-48)Online publication date: 21-Jan-2003
https://dl.acm.org/doi/10.1145/1119772.1119781
Abbaspour SPedram M(2003)Calculating the effective capacitance for the RC interconnect in VDSM technologiesProceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.10.1109/ASPDAC.2003.1194991(43-48)Online publication date: 2003
https://doi.org/10.1109/ASPDAC.2003.1194991
Yang XCheng CKu WCarragher R(2002)Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz PolynomialAnalog Integrated Circuits and Signal Processing10.1023/A:101534052344331:3(193-208)Online publication date: 2-May-2002
https://dl.acm.org/doi/10.1023/A%3A1015340523443
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