Article

Free access

Optimization of combinational logic circuits based on compatible gates

Authors:

Maurizio Damiani,

Jerry Chih-Yuan Yang,

Giovanni De MicheliAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 631 - 636

https://doi.org/10.1145/157485.165073

Published: 01 July 1993 Publication History

PDF eReader

References

[1]

R. Rudell and A. Sangiovanni-Vincentelli, "Multiple-valued minimization for PLA optimization," IEEE Transactions on CAD/ICAS, vol. 6, no. 5, pp. 727-750, Sept. 1987.

Digital Library

Google Scholar

[2]

E.L. Lawler, "An approachto multilevel boolean minimization," ACM Journal, voi. 11, no. 3, pp. 283-295, July 1964.

Digital Library

Google Scholar

[3]

R.K. Brayton, R. Rudell, A. Sangiovanni-Vincentelfi, andA. R. Wang, "MIS: A multiple-level logic optimization system," IEEE Transactions on CAD/ICAS, vol. 6, no. 6, pp. 1062-1081, Nov. 1987.

Digital Library

Google Scholar

[4]

S. Muroga, Y. Kambayashi, H. C. Lai, and J. N. Culliney, "The transduction method - design of logic networks based on permissible functions," IEEE Transactions on Computers, vol. 38, no. 10, pp. 1404- 1424, Oct. 1989.

Digital Library

Google Scholar

[5]

K. A. Bartlett, R. K. Brayton, G. D. Hachtel, R. M. Jacoby, C. R. Morrison, R. L. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, "Multilevel logic minimization using implicit don't cares," IEEE Transactions on CAD/ICAS, vol. 7, no. 6, pp. 723-740, June 1988.

Digital Library

Google Scholar

[6]

R. Brayton and F. Somenzi, "An exact minimizer for boolean relations," in ICCAD, Proceedings of the International Conference on Computer-Aided Design, pp. 316-319, Nov. 1989.

Google Scholar

[7]

E.J. McCluskey, Logic Design Principles With Emphasis on Testable Semicustom Circuits. Prentice-Hall, 1986.

Digital Library

Google Scholar

[8]

S.W. Jeong and E Somenzi, "A new algorithm for the binate coveting problem and its application to the minimization of boolean relations," in ICCAD, Proceedings of the International Conference on Computer. Aided Design, pp. 417-420, 1992.

Digital Library

Google Scholar

[9]

M. Damiani, J. Yang, and G. De Micheli, "Optimization of combinational logic circuits based on compatible gates," tech. rep., Computer Systems Laboratory, Stanford University, 1993.

Digital Library

Google Scholar

[10]

g. E. Bryant, "'Ciraph-based algorithms l~or boolean function manipulation," IEEE Transactions on Computers, vol. 35, no. 8, pp. 677-691, Aug. 1986.

Digital Library

Google Scholar

[11]

H. Savoj, R. K. Brayton, and H. Touati, "Extracting local don't cares and network optimization," in ICCAD, Proceedings of the International Conference on Computer-Aided Design, pp. 514-517, Nov. 1991.

Crossref

Google Scholar

Cited By

View all

Chang SWu Z(2006)Theorems and extensions of single wire replacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.94531020:9(1159-1164)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.945310
Kunz WStoffel DMenon P(2006)Logic optimization and equivalence checking by implication analysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.59483216:3(266-281)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.594832
Watanabe YGuerra LBrayton R(2006)Permissible functions for multioutput components in combinational logic optimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.50394215:7(732-744)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.503942
Show More Cited By

Index Terms

Optimization of combinational logic circuits based on compatible gates

Recommendations

Quaternary CMOS Combinational Logic Circuits
ICIMT '09: Proceedings of the 2009 International Conference on Information and Multimedia Technology

Good Characteristics and advantages of multi-valued logic (MVL) electronic systems and circuits are created great interest for its practical implementation. This paper presents voltage mode quaternary CMOS circuit design using 90nm technology. Basic ...
Optimization of Combinational Logic Circuits Based on Compatible Gates
Design of Memristor-Based Combinational Logic Circuits
Abstract
This paper proposes three modified memristor ratioed logic (MRL) gates: NOT, NOR and A AND (NOR B) (i.e., $A \cdot \bar{B}$ ), each of which only needs 1 memristor and 1 NMOS. Based on the modified MRL gates, we design some combinational logic circuits, ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 July 1993

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

DAC93

Sponsor:

EDAC
SIGDA
IEEE-CAS

DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

Acceptance Rates

Overall Acceptance Rate 299 of 1,119 submissions, 27%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

10
Total Citations
View Citations
314
Total Downloads

Downloads (Last 12 months)28
Downloads (Last 6 weeks)5

Reflects downloads up to 16 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Chang SWu Z(2006)Theorems and extensions of single wire replacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.94531020:9(1159-1164)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.945310
Kunz WStoffel DMenon P(2006)Logic optimization and equivalence checking by implication analysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.59483216:3(266-281)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.594832
Watanabe YGuerra LBrayton R(2006)Permissible functions for multioutput components in combinational logic optimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.50394215:7(732-744)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.503942
Chang SChuang JWu ZWhite JSentovich E(1999)Synthesis for multiple input wires replacement of a gate for wiring considerationProceedings of the 1999 IEEE/ACM international conference on Computer-aided design10.5555/339492.339599(115-119)Online publication date: 7-Nov-1999
https://dl.acm.org/doi/10.5555/339492.339599
Shih-Chieh Chang Jung-Cheng Chuang Zhong-Zhen Wu (1999)Synthesis for multiple input wires replacement of a gate for wiring consideration1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)10.1109/ICCAD.1999.810633(115-118)Online publication date: 1999
https://doi.org/10.1109/ICCAD.1999.810633
Chang Svan Ginneken LMarek-Sadowska MRutenbar ROtten R(1997)Fast Boolean optimization by rewiringProceedings of the 1996 IEEE/ACM international conference on Computer-aided design10.5555/244522.244568(262-269)Online publication date: 1-Jan-1997
https://dl.acm.org/doi/10.5555/244522.244568
Shih-Chieh Chang van Ginneken LMarek-Sadowska M(1996)Fast Boolean optimization by rewiringProceedings of International Conference on Computer Aided Design10.1109/ICCAD.1996.569641(262-269)Online publication date: 1996
https://doi.org/10.1109/ICCAD.1996.569641
Chang SMarek-Sadowska MCheng K(1996)Perturb and simplifyIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.55208215:12(1494-1504)Online publication date: 1-Dec-1996
https://dl.acm.org/doi/10.1109/43.552082
Chang SMarek-Sadowska MJess JRudell R(1994)Perturb and simplifyProceedings of the 1994 IEEE/ACM international conference on Computer-aided design10.5555/191326.191333(2-5)Online publication date: 6-Nov-1994
https://dl.acm.org/doi/10.5555/191326.191333
Shih-Chieh Chang Marek-Sadowska M(1984)Perturb And Simplify: Multi-level Boolean Network OptimizerIEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.1994.629734(2-5)Online publication date: 1984
https://doi.org/10.1109/ICCAD.1994.629734

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Quaternary CMOS Combinational Logic Circuits

Optimization of Combinational Logic Circuits Based on Compatible Gates

Design of Memristor-Based Combinational Logic Circuits