A verification technique for gated clock

Clock skew scheduling is a common and well known technique to improve the performance of sequential circuits by exploiting the mismatches in the data path delays. Existing clock skew scheduling techniques, however, cannot effectively consider heavily ...

Clock gating is one of the most effective techniques to reduce clock network power dissipation. Although it has already been studied considerably, most of the previous works are restricted to either logic level or clock routing stage. Due to the ...

This paper presents a clock polarity assignment flow which permits post-silicon reconfigurability. The proposed method inserts XOR gates at one level of the clock tree to facilitate the polarity assignment. The polarity of the XOR gates can be ...