Article

Free access

An architectural framework for migration from CISC to higher performance platforms

Authors:

Gabriel M. Silberman,

Kemal EbcioğluAuthors Info & Claims

ICS '92: Proceedings of the 6th international conference on Supercomputing

Pages 198 - 215

https://doi.org/10.1145/143369.143410

Published: 01 August 1992 Publication History

Abstract

We describe a novel architectural framework that allows software applications written for a given Complex Instruction Set Computer (CISC) to migrate to a different, higher performance architecture, without a significant investment on the part of the application user or developer. The framework provides a hardware mechanism for seamless switching between two instruction sets, resulting in a machine that enhances application performance while keeping the same program behavior (from a user perspective). High execution speed on migrated applications is achieved through automated translation of the object code of one machine to that of the other, using advanced global optimization and scheduling techniques. Issues affecting application behavior, such as precise exceptions, as well as self-modifying code, are addressed. Relaxation of full compatibility on these issues lead to further possible performance gains, encouraging applications to adopt the newer architecture.

The proposed framework offers a path for moving from complex instruction set computers (CISCs) to newer architectures, such as reduced instruction set computers (RISCs), superscalars, or very long instruction word (VLIW) machines, while protecting the extensive economic investment represented by existing software. To illustrate our approach, we show how system code written (and compiled) for the IBM System/390 can yield fine-grain parallelism, as it is targeted for execution by a VLIW machine, with encouraging performance results.

References

[1]

Agerwala, T. and Cocke, J., "ttigh Performance Reduced Instruction Set Computers," Research Report RC-12434, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, 1987.

[2]

Aho, A., Sethi R., and Ullman, J., Compiler Principles, Techniques, and Tools, Addison-Wesley, 1986.

Digital Library

[3]

Bhandarkar, D., and Clark, D.W., "Performance from Architecture: Comparing a RISC and a CISC with Similar Hardware Organization," Proc. 4th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-I V), Santa Clara, CA, April 1991, pp. 310-319.

Digital Library

[4]

Colwell, R.P., Nix, R.P., O'Donnell, J.J., Papworth, D.B., and Rodman, P.K., "A VLIW Architecture for a Trace Scheduling Compiler," Proc. 2nd International Conference on Architectural Support for Programming Languages and Operating,Systems (ASPLOS-H), Palo Alto, CA, October 1987, pp. 180-192.

Digital Library

[5]

Ebcioglu, K., "Some Design Ideas for a VLIW Architecture for Sequential Natured Software," in Parallel Processing (Proceedings of IFIP WG 10.3 Working Conference on Parallel Processing), M. Cosnard et al. (eds.), pp. 3-21, North HollandL, 1988.

[6]

Ebcioglu, K. and Groves, R., "Some Global Compiler Optimizations and Architectural Features for Improving Performance of Superscalars," Research Report RC-16145, IBM T.J. Watson Research Center, 1990.

[7]

Ebcioglu, K., and Nakatani, T., "A New Compilation Technique for Parallelizing Loops with Unpredictable Branches on a VLIW Architecture," in Languages and Compilers for Parallel Computing, D. Gelernter, A. Nicolau, and D. Padua (eds.), Research Monographs in Parallel and Distributed Computing, pp. 213-229, MIT Press, 1990.

Digital Library

[8]

Ellis, J., Bulldog: A Compiler for VLIW Architectures, MIT Press, 1986.

Digital Library

[9]

Emma, P.G., Knight, J.W., Pomerene, J.H., Rechtschaffen, R.N., and Sparacio, F.J., "Posting out-of-sequence fetches," United States Patent 4,991,090, February 1991.

[10]

Hwu, W. and Patt, Y.N., "Checkpoint Repair for High-Performance Out-of-Order Execution Machines," IEEE Trans. Cornput. C-36(12), December 1987, pp. 1496-1514.

Digital Library

[11]

IBM Corporation, IBM RISC System/6000 Technology, Publication number SA23-2619, Mechanicsburg, PA, 1990.

[12]

IBM Corporation, ESA}390 Principles of Operation, Manual no. SA22-7201, Mechanicsburg, PA.

[13]

Katz, R.H., et al, "Implementing a Cache Consistency Protocol," 12th International Symposium on Computer Architecture, Boston, MA, June 1985, pp. 276-283.

Digital Library

[14]

Nakatanl T., and Ebcioglu, K., "Using a Lookahead Window in a Compaction Based Parallelizing Compiler," Proc. 23rd Workshop on Microprogramming and Microarchitecture, IEEE Computer Society Press, November 1990, pp. 57-68.

Digital Library

[15]

Nicolau, A., "Percolation Scheduling: A Parallel Compilation Technique," TR 85-678, Dept. of Computer Science, Cornell University, May 1985.

Digital Library

[16]

Nicolau, A., "Run-time Disambiguation: Coping with Statically Unpredictable Dependencies," IEEE Trans. Comput. 38(5), May 1989, pp. 663-678.

Digital Library

[17]

Smith, J.E. and Pleszkun, A.R., "Implementing Precise interrupts in Pipelined Processors," 1EEE Trans. Comput. 37(5), May 1988, pp. 562-573.

Digital Library

[18]

Sohi, G.S., "Instruction Issue Logic for High Performance, lnterruptible, Multiple Functional Unit, Pipelined Computers," IEEE Trans. Comput. 39(3), March 1990, pp. 349-359.

Digital Library

[19]

Warren, .S.H., Auslander, M.A., Chaitin, G.J., Chibib, A.C., Hopkins, M.E., and MacKay, A.L., "Final Code Generation in tile PL.8 Compiler," Research Report RC-11974, IBM Thomas J. Watson Research Center, 1986.

[20]

Wegman, M.N., "Fast Emulation with Compiled Look-Aside Information," Research Report RC-7580, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, 1979.

Cited By

Ebcioglu KAltman EGschwind MSathaye S(2001)Dynamic Binary Translation and OptimizationIEEE Transactions on Computers10.1109/12.93189250:6(529-548)Online publication date: 1-Jun-2001
https://dl.acm.org/doi/10.1109/12.931892
Gschwind MEbcioğlu KAltman ESathaye SReynders JVeidenbaum A(2000)Binary translation and architecture convergence issues for IBM system/390Proceedings of the 14th international conference on Supercomputing10.1145/335231.335264(336-347)Online publication date: 8-May-2000
https://dl.acm.org/doi/10.1145/335231.335264
Conte TSathaye S(2000)Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation CompatibilityIEEE Transactions on Computers10.1109/12.86802749:8(814-825)Online publication date: 1-Aug-2000
https://dl.acm.org/doi/10.1109/12.868027
Show More Cited By

Index Terms

Recommendations

RISC versus CISC: a tale of two chips

This paper compares an aggressive RISC and CISC implementation built with comparable technology. The two chips are the Alpha^* 21164 and the Intel Pentium® Pro processor. The paper presents performance comparisons for industry standard benchmarks and ...
Enhanced code density of embedded CISC processors with echo technology
CODES+ISSS '05: Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even at the cost of significant performance loss. In this paper, we develop an ...
Novel task migration framework on configurable heterogeneous MPSoC platforms
ASP-DAC '09: Proceedings of the 2009 Asia and South Pacific Design Automation Conference

Heterogeneous MPSoC architectures can provide higher performance and flexibility with less power consumption and lower cost than homogeneous ones. However, as processor instruction sets of general heterogeneous MPSoCs are not identical, tasks migration ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

ICS '92: Proceedings of the 6th international conference on Supercomputing

August 1992

495 pages

ISBN:0897914856

DOI:10.1145/143369

Chairmen:
Ken Kennedy
Rice University, Houston, TX
,
Constantine D. Polychronopoulos
Kubota Pacific Computers and CSRD

Copyright © 1992 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 August 1992

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

ICS92

Sponsor:

SIGARCH

ICS92: ACM SIGARCH International Conference on Supercomputing

July 19 - 24, 1992

D. C., Washington, USA

Acceptance Rates

Overall Acceptance Rate 629 of 2,180 submissions, 29%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

15
Total Citations
View Citations
545
Total Downloads

Downloads (Last 12 months)86
Downloads (Last 6 weeks)11

Reflects downloads up to 13 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

Ebcioglu KAltman EGschwind MSathaye S(2001)Dynamic Binary Translation and OptimizationIEEE Transactions on Computers10.1109/12.93189250:6(529-548)Online publication date: 1-Jun-2001
https://dl.acm.org/doi/10.1109/12.931892
Gschwind MEbcioğlu KAltman ESathaye SReynders JVeidenbaum A(2000)Binary translation and architecture convergence issues for IBM system/390Proceedings of the 14th international conference on Supercomputing10.1145/335231.335264(336-347)Online publication date: 8-May-2000
https://dl.acm.org/doi/10.1145/335231.335264
Conte TSathaye S(2000)Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation CompatibilityIEEE Transactions on Computers10.1109/12.86802749:8(814-825)Online publication date: 1-Aug-2000
https://dl.acm.org/doi/10.1109/12.868027
Ebcioğlu KAltman ESathaye SGschwind M(1999)Execution-Based Scheduling for VLIW ArchitecturesEuro-Par’99 Parallel Processing10.1007/3-540-48311-X_181(1269-1280)Online publication date: 6-Aug-1999
https://doi.org/10.1007/3-540-48311-X_181
Ebcioğlu KAltman E(1997)DAISYACM SIGARCH Computer Architecture News10.1145/384286.26412625:2(26-37)Online publication date: 1-May-1997
https://dl.acm.org/doi/10.1145/384286.264126
Ebcioğlu KAltman EPleszkun AMudge T(1997)DAISYProceedings of the 24th annual international symposium on Computer architecture10.1145/264107.264126(26-37)Online publication date: 1-Jun-1997
https://dl.acm.org/doi/10.1145/264107.264126
Conte TSathaye SBanerjia SMelvin SBeaty S(1996)A persistent rescheduled-page cache for low overhead object code compatibility in VLIW architecturesProceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture10.5555/243846.243850(4-13)Online publication date: 2-Dec-1996
https://dl.acm.org/doi/10.5555/243846.243850
Conte TSathaye SBanerjia S(1996)A persistent rescheduled-page cache for low overhead object code compatibility in VLIW architecturesProceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 2910.1109/MICRO.1996.566445(4-13)Online publication date: 1996
https://doi.org/10.1109/MICRO.1996.566445
Franklin MSohi G(1996)ARBIEEE Transactions on Computers10.1109/12.50990745:5(552-571)Online publication date: 1-May-1996
https://dl.acm.org/doi/10.1109/12.509907
Cogswell BSegall ZBic LEvripidou PBöhm WGaudiot J(1995)Performance impact of architectural features during binary to binary translationProceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques10.5555/224659.224957(302-305)Online publication date: 27-Jun-1995
https://dl.acm.org/doi/10.5555/224659.224957
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Figures

Tables

Media

View Table of Conten