research-article

iFill: an impact-oriented X-filling method for shift- and capture-power reduction in at-speed scan-based testing

Authors:

Xiaowei LiAuthors Info & Claims

DATE '08: Proceedings of the conference on Design, automation and test in Europe

Pages 1184 - 1189

https://doi.org/10.1145/1403375.1403663

Published: 10 March 2008 Publication History

Abstract

In scan-based tests, power consumptions in both shift and capture phases may be significantly higher than that in normal mode, which threatens circuits' reliability during manufacturing test. In this paper, by analyzing the impact of X-bits on circuit switching activities, we present an X-filling technique that can decrease both shift- and capture-power to guarantees the reliability of scan tests, called iFill. Moreover, different from prior work on X-filling for shift-power reduction which can only reduce shift-in power, iFill is able to decrease power consumptions during both shift-in and shift-out. Experimental results on ISCAS'89 benchmark circuits show the effectiveness of the proposed technique.

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Cited By

Govindaraj VManoharan KPrabha KDhanasekar SSreekanth K(2022)Minimum Power Test Pattern Generator for Testing VLSI Circuits2022 6th International Conference on Devices, Circuits and Systems (ICDCS)10.1109/ICDCS54290.2022.9780773(27-31)Online publication date: 21-Apr-2022
https://doi.org/10.1109/ICDCS54290.2022.9780773
Zhang YWen XHolst SMiyase KKajihara SWunderlich HQian J(2018)Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing2018 IEEE 27th Asian Test Symposium (ATS)10.1109/ATS.2018.00037(149-154)Online publication date: Oct-2018
https://doi.org/10.1109/ATS.2018.00037
Vartziotis FKavousianos X(2017)Critical pathProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130534(642-645)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130534
Show More Cited By

Index Terms

iFill: an impact-oriented X-filling method for shift- and capture-power reduction in at-speed scan-based testing
1. Hardware

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cover image ACM Conferences

DATE '08: Proceedings of the conference on Design, automation and test in Europe

March 2008

1575 pages

ISBN:9783981080131

DOI:10.1145/1403375

General Chair:
Donatella Sciuto
Politecnico di Milano, Italy

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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The Russian Academy of Sciences: The Russian Academy of Sciences

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Association for Computing Machinery

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Published: 10 March 2008

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DATE '08: Design, Automation and Test in Europe

March 10 - 14, 2008

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Citations

Cited By

Govindaraj VManoharan KPrabha KDhanasekar SSreekanth K(2022)Minimum Power Test Pattern Generator for Testing VLSI Circuits2022 6th International Conference on Devices, Circuits and Systems (ICDCS)10.1109/ICDCS54290.2022.9780773(27-31)Online publication date: 21-Apr-2022
https://doi.org/10.1109/ICDCS54290.2022.9780773
Zhang YWen XHolst SMiyase KKajihara SWunderlich HQian J(2018)Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing2018 IEEE 27th Asian Test Symposium (ATS)10.1109/ATS.2018.00037(149-154)Online publication date: Oct-2018
https://doi.org/10.1109/ATS.2018.00037
Vartziotis FKavousianos X(2017)Critical pathProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130534(642-645)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130534
Vartziotis FKavousianos X(2017)Critical path — Oriented & thermal aware X-filling for high un-modeled defect coverageDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927067(642-645)Online publication date: Mar-2017
https://doi.org/10.23919/DATE.2017.7927067
Cheng KWang LLi HLi J(2016)Automatic Test Pattern GenerationElectronic Design Automation for IC System Design, Verification, and Testing10.1201/b19569-28(559-604)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19569-28
Ding WHsieh HHan CLi JWen X(2016)Test Pattern Modification for Average IR-Drop ReductionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.239129124:1(38-49)Online publication date: Jan-2016
https://doi.org/10.1109/TVLSI.2015.2391291
Chen FChen SLin YHwang T(2012)A physical-location-aware X-bit redistribution for maximum IR-drop reductionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.217336120:12(2255-2264)Online publication date: 1-Dec-2012
https://dl.acm.org/doi/10.1109/TVLSI.2011.2173361
Sivanantham SSarathkumar KManuel JMallick PPerinbam J(2012)CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications2012 International Symposium on Electronic System Design (ISED)10.1109/ISED.2012.62(135-139)Online publication date: Dec-2012
https://doi.org/10.1109/ISED.2012.62
Wang WKuang JYou Z(2012)Achieving low capture and shift power in linear decompressor-based test compression environmentMicroelectronics Journal10.1016/j.mejo.2011.10.01243:2(134-140)Online publication date: Feb-2012
https://doi.org/10.1016/j.mejo.2011.10.012
Wen XZorian Y(2012)Low‐Power Testing for Low‐Power LSI CircuitsAdvanced Circuits for Emerging Technologies10.1002/9781118181508.ch20(509-528)Online publication date: 7-May-2012
https://doi.org/10.1002/9781118181508.ch20
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