research-article

CoMPSoC: A template for composable and predictable multi-processor system on chips

Authors:

Andreas Hansson,

Jos HuiskenAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 14, Issue 1

Article No.: 2, Pages 1 - 24

https://doi.org/10.1145/1455229.1455231

Published: 23 January 2009 Publication History

Abstract

A growing number of applications, often with firm or soft real-time requirements, are integrated on the same System on Chip, in the form of either hardware or software intellectual property. The applications are started and stopped at run time, creating different use-cases. Resources, such as interconnects and memories, are shared between different applications, both within and between use-cases, to reduce silicon cost and power consumption.

The functional and temporal behaviour of the applications is verified by simulation and formal methods. Traditionally, designers resort to monolithic verification of the system as whole, since the applications interfere in shared resources, and thus affect each other's behaviour. Due to interference between applications, the integration and verification complexity grows exponentially in the number of applications, and the task to verify correct behaviour of concurrent applications is on the system designer rather than the application designers.

In this work, we propose a Composable and Predictable Multi-Processor System on Chip (CoMPSoC) platform template. This scalable hardware and software template removes all interference between applications through resource reservations. We demonstrate how this enables a divide-and-conquer design strategy, where all applications, potentially using different programming models and communication paradigms, are developed and verified independently of one another. Performance is analyzed per application, using state-of-the-art dataflow techniques or simulation, depending on the requirements of the application. These results still apply when the applications are integrated onto the platform, thus separating system-level design and application design.

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Index Terms

CoMPSoC: A template for composable and predictable multi-processor system on chips
1. Hardware
  1. Hardware validation

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cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 14, Issue 1

January 2009

444 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1455229

Issue’s Table of Contents

Copyright © 2009 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 23 January 2009

Accepted: 01 August 2008

Revised: 01 March 2008

Received: 01 September 2007

Published in TODAES Volume 14, Issue 1

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https://dl.acm.org/doi/10.1145/3582006
Tadepalli SWu ZPatel H(2023)PASoC: A Predictable Accelerator-rich SoCProceedings of Cyber-Physical Systems and Internet of Things Week 202310.1145/3576914.3587496(325-330)Online publication date: 9-May-2023
https://dl.acm.org/doi/10.1145/3576914.3587496
de Lecea AHassan MMezzetti EAbella JCazorla F(2023)Improving Timing-Related Guarantees for Main Memory in Multicore Critical Embedded Systems2023 IEEE Real-Time Systems Symposium (RTSS)10.1109/RTSS59052.2023.00031(265-278)Online publication date: 5-Dec-2023
https://doi.org/10.1109/RTSS59052.2023.00031
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