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The DASH prototype: implementation and performance

Authors:

Daniel Lenoski,

David Nakahira,

John HennessyAuthors Info & Claims

ISCA '92: Proceedings of the 19th annual international symposium on Computer architecture

Pages 92 - 103

https://doi.org/10.1145/139669.139706

Published: 01 April 1992 Publication History

Abstract

The fundamental premise behind the DASH project is that it is feasible to build large-scale shared-memory multiprocessors with hardware cache coherence. While paper studies and software simulators are useful for understanding many high-level design trade-offs, prototypes are essential to ensure that no critical details are overlooked. A prototype provides convincing evidence of the feasibility of the design allows one to accurately estimate both the hardware and the complexity cost of various features, and provides a platform for studying real workloads. A 16-processor prototype of the DASH multiprocessor has been operational for the last six months. In this paper, the hardware overhead of directory-based cache coherence in the prototype is examined. We also discuss the performance of the system, and the speedups obtained by parallel applications running on the prototype. Using a sophisticated hardware performance monitor, we characterize the effectiveness of coherent caches and the relationship between an application's reference behavior and its speedup.

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Index Terms

The DASH prototype: implementation and performance
1. Computer systems organization
  1. Architectures
    1. Parallel architectures

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The DASH Prototype: Logic Overhead and Performance

The fundamental premise behind the DASH project is that it is feasible to build large-scale shared-memory multiprocessors with hardware cache coherence. The hardware overhead of directory-based cache coherence in a 48-processor is examined. The data ...
The DASH prototype: implementation and performance
Special Issue: Proceedings of the 19th annual international symposium on Computer architecture (ISCA '92)

The fundamental premise behind the DASH project is that it is feasible to build large-scale shared-memory multiprocessors with hardware cache coherence. While paper studies and software simulators are useful for understanding many high-level design ...
The DASH prototype: logic overhead and performance
Multiprocessor performance measurement and evaluation

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Information

Published In

cover image ACM Conferences

ISCA '92: Proceedings of the 19th annual international symposium on Computer architecture

May 1992

439 pages

ISBN:0897915097

DOI:10.1145/139669

Chairman:
Allan Gottlieb
New York Unvi., New York, NY

ACM SIGARCH Computer Architecture News Volume 20, Issue 2
Special Issue: Proceedings of the 19th annual international symposium on Computer architecture (ISCA '92)
May 1992
429 pages
ISSN:0163-5964
DOI:10.1145/146628
Editor:
Allan Gotlieb
New York Univ., New York, NY
Issue’s Table of Contents

Copyright © 1992 Authors.

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SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS: Computer Society

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 April 1992

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ISCA92

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ISCA92: International Conference on Computer Architecture

May 19 - 21, 1992

Queensland, Australia

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Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Fan MTruong K(2018)Guidelines for Creating Senior-Friendly Product InstructionsACM Transactions on Accessible Computing10.1145/320988211:2(1-35)Online publication date: 8-Jun-2018
https://dl.acm.org/doi/10.1145/3209882
Zhang LFu QSwanson AWeitlauf AWarren ZSarkar N(2018)Design and Evaluation of a Collaborative Virtual Environment (CoMove) for Autism Spectrum Disorder InterventionACM Transactions on Accessible Computing10.1145/320968711:2(1-22)Online publication date: 8-Jun-2018
https://dl.acm.org/doi/10.1145/3209687
Malas THager GLtaief HKeyes D(2017)Multidimensional Intratile Parallelization for Memory-Starved Stencil ComputationsACM Transactions on Parallel Computing10.1145/31552904:3(1-32)Online publication date: 18-Dec-2017
https://dl.acm.org/doi/10.1145/3155290
Diener MCruz EAlves MNavaux PKoren I(2016)Affinity-Based Thread and Data Mapping in Shared Memory SystemsACM Computing Surveys10.1145/300638549:4(1-38)Online publication date: 5-Dec-2016
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Gornish EGranston EVeidenbaum A(2014)Author retrospective for compiler-directed data prefetching in multiprocessors with memory hierarchiesACM International Conference on Supercomputing 25th Anniversary Volume10.1145/2591635.2591644(9-11)Online publication date: 10-Jun-2014
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Fröning HSilla FMontaner H(2013)MEMSCALE: Re-architecting Memory Resources for ClustersHigh-Performance Computing Using FPGAs10.1007/978-1-4614-1791-0_19(569-604)Online publication date: 28-Feb-2013
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Jiang WCotton CChang SEllis DLoui A(2010)Audio-visual atoms for generic video concept classificationACM Transactions on Multimedia Computing, Communications, and Applications10.1145/1823746.18237486:3(1-19)Online publication date: 27-Aug-2010
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Kunz RHorowitz MBerger EChen B(2008)The case for simple, visible cache coherencyProceedings of the 2008 ACM SIGPLAN workshop on Memory systems performance and correctness: held in conjunction with the Thirteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '08)10.1145/1353522.1353532(31-35)Online publication date: 2-Mar-2008
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