research-article

Power-gating-aware high-level synthesis

Authors:

Youngsoo ShinAuthors Info & Claims

ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & Design

Pages 39 - 44

https://doi.org/10.1145/1393921.1393936

Published: 11 August 2008 Publication History

Publisher Site Get Access

Abstract

A problem inherent in designing power-gated circuits is the overhead of the state-retention storage required to preserve the circuit state in standby mode. Reducing the amount of retention storage is known to be the most influential factor in minimizing the loss of the benefit (i.e. power saving) by power-gating. In this paper, we address a new problem of high-level synthesis with the objective of minimizing the size of retention storage to be used in the power-gated circuits. Specifically, we propose a complete design framework, called HLS-pg, that starts from the power-gating-aware scheduling, allocation, and controller synthesis down to the final circuit layout. The key contribution of the work is to solve the power-gating-aware scheduling problem, namely, scheduling operations that minimizes the number of retention registers required at the power-gating control step, while satisfying resource and latency constraints. In experiments on benchmark designs implemented in 65-nm CMOS technology, HLS-pg generates circuits with 27% less leakage current, with 6% less circuit area and wirelength, compared to the power-gated circuits produced by conventional highlevel synthesis.

References

[1]

J. Friedrich et al., "Design of the Power6 microprocessor," in Proc. ISSCC, Feb. 2007, pp. 96--97.

[2]

K. Roy, S. Mukhopadhyay, and H. Mahmoodi Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits," Proceedings of the IEEE, vol. 91, no. 2, pp. 305--327, Feb. 2003.

[3]

S. G. Narendra and A. Chandrakasan, Eds., Leakage in Nanometer CMOS Technologies, Springer, 2005.

Digital Library

[4]

S. Mutoh et al., "A 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE JSSC, vol. 30, no. 8, pp. 847--854, Aug. 1995.

[5]

S. V. Kosonocky et al., "Enhanced multi-threshold (MTCMOS) circuits using variable well bias," in Proc. ISLPED, Aug. 2001, pp. 165--169.

Digital Library

[6]

H.-S. Won et al., "An MTCMOS design methodology and its application to mobile computing," in Proc. ISLPED, Aug. 2003, pp. 110--115.

Digital Library

[7]

P. Royannez et al., "90nm low leakage SoC design techniques for wireless applications," in Proc. ISSCC, Feb. 2006, pp. 138--139.

[8]

H.-O. Kim and Y. Shin, "Semicustom design methodology of power gated circuits for low leakage applications," IEEE TCAS II, vol. 54, no. 6, pp. 512--516, June 2007.

[9]

S. Shigematsu et al., "A 1-V high-speed MTCMOS circuit scheme for powerdown application circuits," IEEE JSSC, vol. 32, no. 6, pp. 861--869, June 1997.

[10]

J. Kao and A. Chandrakasan, "MTCMOS sequential circuits," in Proc. ESSCIRC, Sept. 2001, pp. 317--320.

[11]

V. Zyuban and S. V. Kosonocky, "Low power integrated scan-retention mechanism," in Proc. ISLPED, Aug. 2002, pp. 98--102.

Digital Library

[12]

Y. Shin et al., "Supply switching with ground collapse: simultaneous control of subthreshold and gate leakage current in nanometer-scale CMOS circuits, IEEE TVLSI, vol. 15, no. 7, pp. 758--766, July 2007.

Digital Library

[13]

T. Ahn et al., "Incremental analysis and elaboration of VHDL description," in Proc. APCHDL, Jan. 1996, pp. 128--131.

[14]

J. Jeon et al., "High-level synthesis under multi-cycle interconnect delay," in Proc. ASP-DAC, Jan. 2001, pp. 662--667.

Digital Library

[15]

S. Mutoh et al., "Design method of MTCMOS power switch for low-voltage high-speed LSIs," in Proc. ASP-DAC, Jan. 1999, pp. 113--116.

[16]

Synopsys, "Astro user guide," June 2006.

[17]

Synopsys, "Astro-rail user guide," June 2006.

[18]

T. C. Hu, "Parallel sequencing and assembly line problems," Operations Research, vol. 9, no. 6, pp. 841--848, Dec. 1961.

Digital Library

[19]

C.-T. Hwang, J.-H. Lee, and Y.-C. Hsu, "A formal approach to the scheduling problem in high level synthesis," IEEE TCAD, vol. 10, no. 4, pp. 464--475, Apr. 1991.

Digital Library

[20]

G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, Inc., 1994.

Digital Library

[21]

Daniel Brelaz, "New methods to color the vertices of a graph," Communications of the ACM, vol. 22, no. 4, pp. 251--256, Apr. 1979.

Digital Library

[22]

A. Hashimoto and J. Stevens, "Wire routing by optimizing channel assignment within large apertures," in Proc. Design Automation Workshop, June 1971, pp.155--169.

Digital Library

[23]

F.J. Kurdahi and A.C. Parker, "REAL: a program for register allocation," in Proc. DAC, June 1987, pp. 210--215.

Digital Library

[24]

High level synthesis benchmark," http://bears.ece.ucsb.edu/cad/.

[25]

GNU linear programming kit," http://www.gnu.org/software/glpk/.

Cited By

El-Araby NJantsch A(2022)Reliable Power Efficient Systems through Run-time Reconfiguration2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)10.1109/NEWCAS52662.2022.9841986(347-351)Online publication date: 19-Jun-2022
https://doi.org/10.1109/NEWCAS52662.2022.9841986
Kim TPark HKim T(2021)Allocation of Always-On State Retention Storage for Power Gated Circuits—Steady-State- Driven ApproachIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.304705629:3(499-511)Online publication date: Mar-2021
https://doi.org/10.1109/TVLSI.2020.3047056
Hyun GKim T(2021)Allocation of Multibit Retention Flip-Flops for Power Gated Circuits: Algorithm-Design Unified ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.301324340:5(892-903)Online publication date: May-2021
https://doi.org/10.1109/TCAD.2020.3013243
Show More Cited By

Index Terms

Power-gating-aware high-level synthesis
1. Hardware
  1. Very large scale integration design

Recommendations

Interconnect-aware low-power high-level synthesis

Interconnects (wires, buffers, clock distribution networks, multiplexers, and busses) consume a significant fraction of total circuit power. In this paper, we demonstrate the importance of optimizing on-chip interconnects for power during high-level ...
NBTI-aware power gating for concurrent leakage and aging optimization
ISLPED '09: Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design

Power and reliability are known to be intrinsically conflicting metrics: traditional solutions to improve reliability such as redundancy, increase of voltage levels, and up-sizing of critical devices do contrast with traditional low-power solutions, ...
Power management in high-level synthesis

In this paper, we present a power-management methodology targeted toward high-level synthesis of data-dominated behavioral descriptions. It is founded on the observation that variable assignment can significantly affect power-management opportunities in ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

ISLPED '08: Proceedings of the 2008 international symposium on Low Power Electronics & Design

August 2008

396 pages

ISBN:9781605581095

DOI:10.1145/1393921

General Chairs:
Vijaykrishnan Narayanan
Penn State University
,
C. P. Ravikumar
Texas Instruments
,
Joerg Henkel
Univeristy of Karlsruhe
,
Ali Keshavarzi
Intel Corporation
,
Program Chairs:
Vojin G. Oklobdzija
University of Texas at Dallas
,
Barry Pangrle
Pangrle Consulting

Copyright © 2008 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 11 August 2008

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

ISLPED08

Sponsor:

ISLPED08: International Symposium on Low Power Electronics and Design

August 11 - 13, 2008

Bangalore, India

Acceptance Rates

Overall Acceptance Rate 398 of 1,159 submissions, 34%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

28
Total Citations
View Citations
397
Total Downloads

Downloads (Last 12 months)9
Downloads (Last 6 weeks)0

Reflects downloads up to 16 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

El-Araby NJantsch A(2022)Reliable Power Efficient Systems through Run-time Reconfiguration2022 20th IEEE Interregional NEWCAS Conference (NEWCAS)10.1109/NEWCAS52662.2022.9841986(347-351)Online publication date: 19-Jun-2022
https://doi.org/10.1109/NEWCAS52662.2022.9841986
Kim TPark HKim T(2021)Allocation of Always-On State Retention Storage for Power Gated Circuits—Steady-State- Driven ApproachIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.304705629:3(499-511)Online publication date: Mar-2021
https://doi.org/10.1109/TVLSI.2020.3047056
Hyun GKim T(2021)Allocation of Multibit Retention Flip-Flops for Power Gated Circuits: Algorithm-Design Unified ApproachIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.301324340:5(892-903)Online publication date: May-2021
https://doi.org/10.1109/TCAD.2020.3013243
Kim THyun GKim TAlonso DQiu QReda SChen Y(2020)Steady state driven power gating for lightening always-on state retention storageProceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design10.1145/3370748.3406556(79-84)Online publication date: 10-Aug-2020
https://dl.acm.org/doi/10.1145/3370748.3406556
Fan GLin MParameswaran S(2017)State retention for power gated design with non-uniform multi-bit retention latchesProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199781(607-614)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199781
Fan GLin M(2017)State retention for power gated design with non-uniform multi-bit retention latches2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2017.8203833(607-614)Online publication date: Nov-2017
https://doi.org/10.1109/ICCAD.2017.8203833
Wang NChen SMa ZLing XZhu Y(2017)Integrating operation scheduling and binding for functional unit power-gating in high-level synthesisIntegration, the VLSI Journal10.1016/j.vlsi.2017.11.008Online publication date: Dec-2017
https://doi.org/10.1016/j.vlsi.2017.11.008
Zhang ZChen DDai SCampbell K(2015)High-level Synthesis for Low-power DesignIPSJ Transactions on System LSI Design Methodology10.2197/ipsjtsldm.8.128(12-25)Online publication date: 2015
https://doi.org/10.2197/ipsjtsldm.8.12
Lin SLin MChang Y(2014)More effective power-gated circuit optimization with multi-bit retention registersProceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design10.5555/2691365.2691409(213-217)Online publication date: 3-Nov-2014
https://dl.acm.org/doi/10.5555/2691365.2691409
Chen YGeng HLai KShi YChang S(2014)Multibit Retention Registers for Power Gated DesignsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.229388133:4(507-518)Online publication date: 1-Apr-2014
https://dl.acm.org/doi/10.1109/TCAD.2013.2293881
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents