An MTCMOS design methodology and its application to mobile computing
Proceedings of the 2003 international symposium on Low power electronics and …, 2003•dl.acm.org
The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high
performance and low power design requirements of modern designs. While the low Vth
transistors are used to implement the desired function, the high Vth transistors are used to
cut off the leakage current. In this paper, we (i) examine the effectiveness of the MTCMOS
technology for the Samsung's 0.18? m process,(ii) propose a new special flip-flop which
keeps a valid data during the sleep mode, and (iii) develop a methodology which takes into …
performance and low power design requirements of modern designs. While the low Vth
transistors are used to implement the desired function, the high Vth transistors are used to
cut off the leakage current. In this paper, we (i) examine the effectiveness of the MTCMOS
technology for the Samsung's 0.18? m process,(ii) propose a new special flip-flop which
keeps a valid data during the sleep mode, and (iii) develop a methodology which takes into …
The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of modern designs. While the low Vth transistors are used to implement the desired function, the high Vth transistors are used to cut off the leakage current. In this paper, we (i) examine the effectiveness of the MTCMOS technology for the Samsung's 0.18?m process, (ii) propose a new special flip-flop which keeps a valid data during the sleep mode, and (iii) develop a methodology which takes into account the new design issues related to the MTCMOS technology. Towards validating the proposed technique, a Personal Digital Assistant (PDA) processor has been implemented using the MTCMOS design methodology, and the 0.18?m process. The fabricated PDA processor operates at 333MHz, and consumes about 2?W of leakage power. Whereas the performance of the MTCMOS implementation is the same as that of the generic CMOS implementation, three orders of reduction in the leakage power has been achieved.