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Clock routing for high-performance ICs

Authors:

Michael A. B. Jackson,

Arvind Srinivasan,

E. S. KuhAuthors Info & Claims

DAC '90: Proceedings of the 27th ACM/IEEE Design Automation Conference

Pages 573 - 579

https://doi.org/10.1145/123186.123406

Published: 03 January 1991 Publication History

Abstract

In this paper we focus on routing techniques for optimizing clock signals in small-cell (e.g., standard-cell, sea-of gate, etc.…) ASICs. In previously reported work, the routing of the clock net has been performed using ordinary global routing techniques based on a minimum spanning or minimal Steiner tree that have little understanding of clock routing problems. We present a novel approach to clock routing that all but eliminates clock skew and yields excellent phase delay results for a wide range of chip sizes, net sizes (pin count), minimum feature sizes, and pin distributions on both randomly created and standard industrial benchmarks. For certain classes of pin distributions we have proven theoretically and observed experimentally a decrease in skew with an increase in net size. In practice, we have observed a two to three order magnitude reduction in skew when compared to a minimum rectilinear spanning tree.

References

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Cited By

Li XPan MLiu TBeerel P(2022)Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI54635.2022.00024(62-67)Online publication date: Jul-2022
https://doi.org/10.1109/ISVLSI54635.2022.00024
Bairamkulov RFriedman EBairamkulov RFriedman E(2022)Synchronization in VLSIGraphs in VLSI10.1007/978-3-031-11047-4_4(101-147)Online publication date: 30-Jun-2022
https://doi.org/10.1007/978-3-031-11047-4_4
Kahng ALienig JMarkov IHu JKahng ALienig JMarkov IHu J(2022)Specialized RoutingVLSI Physical Design: From Graph Partitioning to Timing Closure10.1007/978-3-030-96415-3_7(195-222)Online publication date: 15-Jun-2022
https://doi.org/10.1007/978-3-030-96415-3_7
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Index Terms

Clock routing for high-performance ICs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Integrated circuits
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory
      1. Trees

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cover image ACM Conferences

DAC '90: Proceedings of the 27th ACM/IEEE Design Automation Conference

January 1991

742 pages

ISBN:0897913639

DOI:10.1145/123186

Chairman:
Richard C. Smith

Copyright © 1991 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS: Computer Society

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 January 1991

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DAC90: The 27th ACM/IEEE-CS Design Automation Conference

June 24 - 27, 1990

Florida, Orlando, USA

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DAC '90 Paper Acceptance Rate 125 of 427 submissions, 29%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Li XPan MLiu TBeerel P(2022)Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI54635.2022.00024(62-67)Online publication date: Jul-2022
https://doi.org/10.1109/ISVLSI54635.2022.00024
Bairamkulov RFriedman EBairamkulov RFriedman E(2022)Synchronization in VLSIGraphs in VLSI10.1007/978-3-031-11047-4_4(101-147)Online publication date: 30-Jun-2022
https://doi.org/10.1007/978-3-031-11047-4_4
Kahng ALienig JMarkov IHu JKahng ALienig JMarkov IHu J(2022)Specialized RoutingVLSI Physical Design: From Graph Partitioning to Timing Closure10.1007/978-3-030-96415-3_7(195-222)Online publication date: 15-Jun-2022
https://doi.org/10.1007/978-3-030-96415-3_7
Zhu LChaudhuri ABanerjee SMurali GVanna-Iampikul PChakrabarty KLim S(2021)Design Automation and Test Solutions for Monolithic 3D ICsACM Journal on Emerging Technologies in Computing Systems10.1145/347346218:1(1-49)Online publication date: 16-Nov-2021
https://dl.acm.org/doi/10.1145/3473462
Li XShahsavani SZhou XPedram MBeerel P(2021)A Variation-aware Hold Time Fixing Methodology for Single Flux Quantum Logic CircuitsACM Transactions on Design Automation of Electronic Systems10.1145/346028926:6(1-17)Online publication date: 1-Aug-2021
https://dl.acm.org/doi/10.1145/3460289
Wang WPavlidis VCheng YMohsenin TZhao WChen YMutlu O(2020)Zero-skew Clock Network Synthesis for Monolithic 3D ICs with Minimum WirelengthProceedings of the 2020 on Great Lakes Symposium on VLSI10.1145/3386263.3406949(399-404)Online publication date: 7-Sep-2020
https://dl.acm.org/doi/10.1145/3386263.3406949
Oh DChoi MKim J(2019)Thermal-aware 3D Symmetrical Buffered Clock Tree SynthesisACM Transactions on Design Automation of Electronic Systems10.1145/331379824:3(1-22)Online publication date: 5-Apr-2019
https://dl.acm.org/doi/10.1145/3313798
Lu TSrivastava A(2017)Low-Power Clock Tree Synthesis for 3D-ICsACM Transactions on Design Automation of Electronic Systems10.1145/301961022:3(1-24)Online publication date: 5-Apr-2017
https://dl.acm.org/doi/10.1145/3019610
(2017)ReferencesThree-Dimensional Integrated Circuit Design10.1016/B978-0-12-410501-0.00033-2(669-707)Online publication date: 2017
https://doi.org/10.1016/B978-0-12-410501-0.00033-2
Guthaus M(2016)Clock Design and SynthesisElectronic Design Automation for IC Implementation, Circuit Design, and Process Technology10.1201/b19714-13(261-282)Online publication date: 14-Apr-2016
https://doi.org/10.1201/b19714-13
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