Article

Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC

Authors:

Brett H. Meyer,

Donald E. ThomasAuthors Info & Claims

CODES+ISSS '07: Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis

Pages 3 - 8

https://doi.org/10.1145/1289816.1289822

Published: 30 September 2007 Publication History

Abstract

Heterogeneous multiprocessors are emerging as the dominant implementation approach to embedded multiprocessor systems. In addition to having processing elements suited to the target applications, these systems will also have custom memory and bus architectures. Because of performance and cost constraints, these systems must be carefully designed to balance system partitioning and resource sharing. The sheer size of the design space requires that tools be able to do this balancing. We have developed an augmented simulated annealing synthesis tool that uses system performance and layout evaluation to drive simultaneous data mapping, memory allocation and bus synthesis. Performing these optimizations at the same time, our tool is able to explore a larger design space and take advantage of cost-saving resource sharing unavailable to previous approaches that allocate memories before synthesizing buses. This results in 20% cost reduction for high-performance designs as well as 27% for low-cost designs in comparison with an approach that performs memory allocation and data mapping separately from bus synthesis.

References

[1]

S. Pasricha, N. Dutt, E. Bozorgzadeh, and M. Ben-Romdhane, "Floorplan-aware automated synthesis of bus-based communication architectures," in DAC '05, 2005.

Digital Library

[2]

S. Pasricha, N. Dutt, and M. Ben-Romdhane, "Constraint-driven bus matrix synthesis for MPSoC," in ASP-DAC '06, 2006.

Digital Library

[3]

S. Pasricha and N. Dutt, "Cosmeca: application specific co-synthesis of memory and communication architectures for MPSoC," in DATE '06, 2006.

Digital Library

[4]

S. Kim, C. Im, and S. Ha, "Eficient exploration of on-chip bus architectures and memory allocation," in CODES+ISSS '04, 2004.

Digital Library

[5]

J. Guo, A. Papanikolaou, P. Marchal, and F. Catthoor, "Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture," in SLIP '06, 2006.

Digital Library

[6]

K. Lahiri, A. Raghunathan, and S. Dey, "Efficient exploration of the soc communication architecture design space," in ICCAD '00, 2000.

Digital Library

[7]

J. Hu, Y. Deng, and R. Marculescu, "System-level point-to-point communication synthesis using floorplanning information," in ASP-DAC '02, 2002.

Digital Library

[8]

S. Maguerdichian, M. Drinic, and D. Kirovski, "Latency-driven design of multi-purpose systems-on-chip," in DAC '01, 2001.

Digital Library

[9]

N. Thepayasuwan and A. Doboli, "Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed," IEEE Trans. on VLSI, vol. 13, no. 5, 2005.

Digital Library

[10]

V. J. Rayward-Smith, I. H. Osman, C. R. Reeves, and G. D. Smith, Modern Heuristic Search Methods. New York, NY, USA: Wiley, 2001.

[11]

M. Huang, F. Romeo, and A. Sangiovanni-Vincentelli, "An efficient general cooling schedule for simulated annealing," in ICCAD '86, 1986.

[12]

D. F. Wong and C. L. Liu, "A new algorithm for floorplan design," in DAC '86, 1986.

Digital Library

[13]

J. Cong and Z. Pan, "Interconnect performance estimation models for design planning," IEEE Trans. on CAD of ICs and Syst., vol. 20, June 2001.

Digital Library

[14]

"ARM7TDMI." http://www.arm.com/products/CPUs/ARM7TDMI.html.

[15]

"CACTI 4.2." http://quid.hpl.hp.com:9081/cacti/.

[16]

B. H. Meyer and D. E. Thomas, "Rethinking automated synthesis of MPSoC architectures," in NSF Next Generation Software Program, March 2007.

Cited By

Cilardo AFusella E(2016)Design automation for application-specific on-chip interconnectsIntegration, the VLSI Journal10.1016/j.vlsi.2015.07.01752:C(102-121)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1016/j.vlsi.2015.07.017
Tsai MChen YChen YChang RFettweis GNebel W(2014)Scenario-aware data placement and memory area allocation for multi-processor system-on-chips with reconfigurable 3D-stacked SRAMsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2617069(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2617069
Lukasiewycz MChakraborty SJerraya ACarloni LChang NFummi F(2012)Concurrent architecture and schedule optimization of time-triggered automotive systemsProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2380445.2380506(383-392)Online publication date: 7-Oct-2012
https://dl.acm.org/doi/10.1145/2380445.2380506
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Index Terms

Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design

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Information & Contributors

Information

Published In

cover image ACM Conferences

CODES+ISSS '07: Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis

September 2007

284 pages

ISBN:9781595938244

DOI:10.1145/1289816

General Chairs:
Soonhoi Ha
Seoul National University, Korea
,
Kiyoung Choi
Seoul National University, Korea
,
Program Chairs:
Nikil Dutt
UC Irvine, USA
,
Jürgen Teich
University of Erlangen-Nuremberg, Germany

Copyright © 2007 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 30 September 2007

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ESWEEK07

Sponsor:

ESWEEK07: Third Embedded Systems Week

September 30 - October 3, 2007

Salzburg, Austria

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Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

Cilardo AFusella E(2016)Design automation for application-specific on-chip interconnectsIntegration, the VLSI Journal10.1016/j.vlsi.2015.07.01752:C(102-121)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1016/j.vlsi.2015.07.017
Tsai MChen YChen YChang RFettweis GNebel W(2014)Scenario-aware data placement and memory area allocation for multi-processor system-on-chips with reconfigurable 3D-stacked SRAMsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2617069(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2617069
Lukasiewycz MChakraborty SJerraya ACarloni LChang NFummi F(2012)Concurrent architecture and schedule optimization of time-triggered automotive systemsProceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2380445.2380506(383-392)Online publication date: 7-Oct-2012
https://dl.acm.org/doi/10.1145/2380445.2380506
Girodias BIugan LBouchebaba YNicolescu GAbouhamid ELangevin MPaulin P(2012)Integrating Memory Optimization with Mapping Algorithms for Multi-Processors System-on-ChipACM Transactions on Embedded Computing Systems10.1145/2345770.234577611:3(1-26)Online publication date: 1-Sep-2012
https://dl.acm.org/doi/10.1145/2345770.2345776
Chen YChiou LChang H(2011)A fast and effective dynamic trace-based method for analyzing architectural performanceProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950933(591-596)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950933
Hazari GNarayanan H(2011)On the Use of Simple Electrical Circuit Techniques for Performance Modeling and Optimization in VLSI SystemsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2010.206050219:10(1861-1873)Online publication date: 1-Oct-2011
https://dl.acm.org/doi/10.1109/TVLSI.2010.2060502
Hazari GDesai MSrinivas G(2010)Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory SystemsProceedings of the 2010 23rd International Conference on VLSI Design10.1109/VLSI.Design.2010.45(15-20)Online publication date: 3-Jan-2010
https://dl.acm.org/doi/10.1109/VLSI.Design.2010.45
Lukasiewycz MStreubühr MGlaß MHaubelt CTeich JBenini LDe Micheli GAl-Hashimi BMueller W(2009)Combined system synthesis and communication architecture exploration for MPSoCsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874737(472-477)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874737
Chiou LChen YLee C(2009)System-level bus-based communication architecture exploration using a pseudoparallel algorithmIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.202173328:8(1213-1223)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2021733
Lukasiewycz MStreubuhr MGlass MHaubelt CTeich J(2009)Combined system synthesis and communication architecture exploration for MPSoCs2009 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2009.5090711(472-477)Online publication date: Apr-2009
https://doi.org/10.1109/DATE.2009.5090711
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