Article

Low area pipelined circuits by multi-clock cycle paths and clock scheduling

Authors:

Bakhtiar Affendi Rosdi,

Atsushi TakahashiAuthors Info & Claims

ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Pages 260 - 265

https://doi.org/10.1145/1118299.1118367

Published: 24 January 2006 Publication History

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Abstract

A new algorithm is proposed to reduce the number of intermediate registers of a pipelined circuit using a combination of multi-clock cycle paths and clock scheduling. The algorithm analyzes the pipelined circuit and determines the intermediate registers that can be removed. An efficient subsidiary algorithm is presented that computes the minimum feasible clock period of a circuit containing multi-clock cycle paths. Experiments with a pipelined adder and multiplier verify that the proposed algorithm can reduce the number of intermediate registers without degrading performance, even when delay variations exist.

References

[1]

W. J. Kim and Y. Kim, "Clocking for correct functionality on wave pipelined circuits," in Proc. IEEE International ASIC/SOC Conference, 2003, pp. 161--164.

Google Scholar

[2]

J. P. Fishburn, "Clock skew optimization," IEEE Trans. on Computers, vol. 39, no. 7, pp. 945--951, 1990.

Digital Library

Google Scholar

[3]

R. B. Deokar and S. S. Sapatnekar, "A graph-theoretic approach to clock skew optimization," in Proc. International Symposium on Circuits and Systems (ISCAS), vol. 1, 1994, pp. 407--410.

Crossref

Google Scholar

[4]

A. Takahashi, "Practical fast clock schedule design algorithms," in Proc. 18th Karuizawa Workshop, 2005, pp. 515--520.

Google Scholar

[5]

A. Takahashi and Y. Kajitani, "Performance and reliability driven clock scheduling of sequential logic circuits," in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), 1997, pp. 37--42.

Crossref

Google Scholar

[6]

B. A. Rosdi and A. Takahashi, "Reduction on the usage of intermediate registers for pipelined circuits," in Proc. the Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2004), 2004, pp. 333--338.

Google Scholar

[7]

S. Malik, K. J. Singh, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Performance optimization of pipelined circuits," in Proc. IEEE/ACM International Conference on Computer Aided Design (ICCAD), 1990, pp. 410--413.

Google Scholar

[8]

C. Wallace, "A suggestion for fast multiplier," IEEE Trans. on Electronic Computers, vol. 13, no. 2, pp. 14--17, 1964.

Crossref

Google Scholar

Index Terms

Low area pipelined circuits by multi-clock cycle paths and clock scheduling
1. Hardware
2. Software and its engineering
  1. Software notations and tools
    1. General programming languages
      1. Language features
        Control structures

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Information

Published In

ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference

January 2006

998 pages

ISBN:0780394518

General Chair:
Fumiyasu Hirose
Cadence Design Systems, Japan

Publisher

IEEE Press

Publication History

Published: 24 January 2006

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