Nothing Special   »   [go: up one dir, main page]

skip to main content
10.1145/1118299.1118368acmconferencesArticle/Chapter ViewAbstractPublication PagesaspdacConference Proceedingsconference-collections
Article

A transduction-based framework to synthesize RSFQ circuits

Published: 24 January 2006 Publication History

Abstract

In this paper, we propose a new framework to synthesize rapid single flux quantum (RSFQ) logic circuits. In our framework, we construct a virtual cell, which we call "2-AND/XOR," from the RSFQ logic primitives. By using 2-AND/XOR cells, we can successfully adopt the conventional logic design techniques into our framework, and thus we can successfully generate RSFQ circuits in reasonable time even for large benchmark circuits that have not been reported in the existing researches.

References

[1]
International Technology Roadmap for Semiconductors. Technical Report http://public.itrs.net/, 2004.
[2]
R. E. Bryant. Graph-based algorithm for Boolean function manipulation. IEEE Transactions on Computers, C-35(8):667--691, August 1986.
[3]
J. Deng, S. Whiteley, and T. Van Duzer, Data-Driven Self-Timing of RSFQ Digital Integrated Circuits. In Extended Abstracts of ISEC'95, pages 189--191, September 1995.
[4]
K. Gaj, E. G. Friedman, and M. J. Feldman. Timing of multi-gigahertz rapid single flux quantum digital circuits. IEEE Journal of VLSI Signal Processing, 16(2-3):247--276, 1997.
[5]
Y. Kameda, S. V. Polonsky, M. Maezawa, and T. Nanya. Self-timed Parallel Adders based on DI RSFQ Primitives. IEEE Trans. Appl. Superconductivity, 9(2):4040--4045, June 1999.
[6]
J. Koshiyama and N. Yoshikawa. A Cell-Based Design Approach for RSFQ Circuits Based on Binary Decision Diagram. IEEE Trans. Appl. Superconductivity, 11(1):263--266, March 2001.
[7]
K. K. Likharev and V. K. Semenov. RSFQ logic/memory family: A new Josephson-junction technology for sub-terahertz-clock frequency digital systems. IEEE Trans. Appl. Superconductivity, 1(1):3--28, March 1991.
[8]
S. Muroga, Y. Kambayashi, H. C. Lai, and J. N. Culliney. The Transduction Method - Design of Logic Networks Based on Permissible Functions. IEEE Transactions on Computers, 38(10):1404--1424, October 1989.
[9]
K. Obata, K. Takagi, and N. Takagi. Design Method of Dual-Rail RSFQ Logic Circuits Using 2x2-Join. IEICE Trans., J88-C(3):202--209, March 2005. (In Japanese)
[10]
H. Savoj and R. K. Brayton. The Use of Observability and External Don't Cares for Simplification of Multi-Level Networks. pages 297--301, June 1990.
[11]
H. Sawada, T. Suyama, and A. Nagoya. Logic Synthesis for Look-up Table Based FPGAs Using Functional Decomposition and Support Minimization. pages 353--358, November 1995.
[12]
V. K. Semenov, Yu. A. Polyakov, and D. Schneider. Implementation of Oversampling Analog-to-Digital Converter Based on RSFQ Logic. In Extended Abstracts of ISEC'97, volume 1, pages 41--43, June 1997.
[13]
E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli. SIS: A System for Sequential Circuit Synthesis. Technical Report UCB/ERL M92/41, Univ. of California, Berkeley, May 1992.
[14]
S. Yamashita, H. Sawada, and A. Nagoya. SPFD: A New Method to Express Functional Permissibilities. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 19(8):840--849, August 2000.
[15]
S. Yang. Logic synthesis and optimization benchmark user guide version 3.0. MCNC, January 1991.
[16]
N. Yoshikawa and J. Koshiyama. Top-Down RSFQ Logic Design Based on a Binary Decision Diagram. IEEE Trans. Appl. Superconductivity, 11(1):1098--1101, March 2001.
[17]
N. Yoshikawa, H. Tago, and K. Yoneyama. A New Design Approach for RSFQ Logic Circuits Based on the Binary Decision Diagram. IEEE Trans. Appl. Superconductivity, 9(2):3161--3164, June 1999.

Cited By

View all
  • (2022)A survey on superconducting computing technology: circuits, architectures and design toolsCCF Transactions on High Performance Computing10.1007/s42514-022-00089-w4:1(1-22)Online publication date: 16-Mar-2022
  • (2010)European roadmap on superconductive electronics – status and perspectivesPhysica C: Superconductivity10.1016/j.physc.2010.07.005470:23-24(2079-2126)Online publication date: Dec-2010

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences
ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference
January 2006
998 pages
ISBN:0780394518

Sponsors

  • IEEE Circuits and Systems Society
  • SIGDA: ACM Special Interest Group on Design Automation
  • IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
  • IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

Publisher

IEEE Press

Publication History

Published: 24 January 2006

Permissions

Request permissions for this article.

Check for updates

Qualifiers

  • Article

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Upcoming Conference

ASPDAC '25

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)0
  • Downloads (Last 6 weeks)0
Reflects downloads up to 30 Nov 2024

Other Metrics

Citations

Cited By

View all
  • (2022)A survey on superconducting computing technology: circuits, architectures and design toolsCCF Transactions on High Performance Computing10.1007/s42514-022-00089-w4:1(1-22)Online publication date: 16-Mar-2022
  • (2010)European roadmap on superconductive electronics – status and perspectivesPhysica C: Superconductivity10.1016/j.physc.2010.07.005470:23-24(2079-2126)Online publication date: Dec-2010

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media