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Multi-processor system design with ESPAM

Published: 22 October 2006 Publication History

Abstract

For modern embedded systems, the complexity of embedded applications has reached a point where the performance requirements of these applications can no longer be supported by embedded system architectures based on a single processor. Thus, the emerging embedded System-on-Chip platforms are increasingly becoming multiprocessor architectures. As a consequence, two major problems emerge, i.e., how to design and how to program such multiprocessor platforms in a systematic and automated way in order to reduce the design time and to satisfy the performance needs of applications executed on these platforms. Unfortunately, most of the current design methodologies and tools are based on Register Transfer Level (RTL) descriptions, mostly created by hand. Such methodologies are inadequate, because creating RTL descriptions of complex multiprocessor systems is error-prone and time consuming.As an efficient solution to these two problems, in this paper we propose a methodology and techniques implemented in a tool called Espam for automated multiprocessor system design and implementation. Espam moves the design specification from RTL to a higher, so called system level of abstraction. We explain how starting from system level platform, application, and mapping specifications, a multiprocessor platform is synthesized and programmed in a systematic and automated way. Furthermore, we present some results obtained by applying our methodology and Espam tool to automatically generate multiprocessor systems that execute a real-life application, namely a Motion-JPEG encoder.

References

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Gilles Kahn, "The Semantics of a Simple Language for Parallel Programming," in Proc. of the IFIP Congress 74. 1974, North-Holland Publishing Co.
[2]
Todor Stefanov et al., "System Design using Kahn Process Networks: The Compaan/Laura Approach," in Proc. Int. Conference Design, Automation and Test in Europe (DATE'04), Paris, France, Feb. 16-20 2004.
[3]
M. J. Rutten et all., "A Heterogeneous Multiprocessor Architecture for Flexible Media Processing," IEEE Design & Test of Computers, vol. 19, no. 4, 2002.
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Andy Pimentel et al., "A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels," IEEE Transactions on Computers, vol. 55, no. 2, 2006.
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Erwin de Kock, "Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study," in Proc. 15th Int. Symposium on System Synthesis, Japan, 2002.
[6]
Kees Goossens et al., "Guaranteeing the Quality Of Services in Networks On Chip," in Networks on Chip. 2003, Kluwer Academic Publishers.
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B. Dwivedi et al., "Automatic Synthesis of System on Chip Multiprocessor Architectures for Process networks," in Proc. Int. Conference on Hardware/Software Codesign and System Synthesis, Sweden, 2004.
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D. Lyonnard et al., "Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip," in Proc. 38th Design Automation Conference (DAC'2001), Las Vegas, USA, June 18-22 2001.
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A. Gerstlauer and D. Gajski, "System-level abstraction semantics," in Proc. 15th Int. Symposium on System Synthesis (ISSS'02), Kyoto, Japan, Oct. 2-4 2002, pp. 231--236.
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Sven Verdoolaege, Hristo Nikolov, and Todor Stefanov, "Improved Derivation of Process Networks," in 4th Workshop on Optimization for DSP and Embedded Systems, ODES-4, New York, USA, Mar. 2006.
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Todor Stefanov and Ed Deprettere, "Deriving Process Networks from Weakly Dynamic Applications in System-Level Design," in Proc. 1th Int. Conf. on Hardware/Software Codesign and System Synthesis, Newport Beach, California, USA, Oct. 1-3 2003, pp. 90--96.

Cited By

View all
  • (2017)Daedalus: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on ChipsHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_30-1(1-36)Online publication date: 11-Apr-2017
  • (2017)DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on ChipsHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_30(983-1018)Online publication date: 27-Sep-2017
  • (2016)TBESACM Transactions on Embedded Computing Systems10.1145/281681715:1(1-27)Online publication date: 13-Jan-2016
  • Show More Cited By

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Published In

cover image ACM Conferences
CODES+ISSS '06: Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
October 2006
328 pages
ISBN:1595933700
DOI:10.1145/1176254
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 22 October 2006

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Author Tags

  1. Kahn process networks
  2. heterogeneous MPSoCs
  3. system-level design

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ESWEEK06
ESWEEK06: Second Embedded Systems Week 2006
October 22 - 25, 2006
Seoul, Korea

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Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

View all
  • (2017)Daedalus: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on ChipsHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_30-1(1-36)Online publication date: 11-Apr-2017
  • (2017)DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on ChipsHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_30(983-1018)Online publication date: 27-Sep-2017
  • (2016)TBESACM Transactions on Embedded Computing Systems10.1145/281681715:1(1-27)Online publication date: 13-Jan-2016
  • (2015)Physical design aware system level synthesis of hardware2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)10.1109/SAMOS.2015.7363669(141-148)Online publication date: Jul-2015
  • (2015)Explicitly isolating data and computation in high level synthesis: the role of polyhedral framework2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)10.1109/ReConFig.2015.7393304(1-6)Online publication date: Dec-2015
  • (2013)System level synthesis of hardware for DSP applications using pre-characterized function implementationsProceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis10.5555/2555692.2555708(1-10)Online publication date: 29-Sep-2013
  • (2013)Multi-ASIP platform synthesis for Event-Triggered applications with cost/performance trade-offs2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications10.1109/RTCSA.2013.6732228(277-286)Online publication date: Aug-2013
  • (2013)System level synthesis of hardware for DSP applications using pre-characterized function implementations2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)10.1109/CODES-ISSS.2013.6659003(1-10)Online publication date: Sep-2013
  • (2013)Efficient communication support in predictable heterogeneous MPSoC designs for streaming applicationsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2013.04.00559:10(878-888)Online publication date: 1-Nov-2013
  • (2013)FPGA-Based DSPHandbook of Signal Processing Systems10.1007/978-1-4614-6859-2_22(707-739)Online publication date: 10-May-2013
  • Show More Cited By

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