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Power-performance trade-offs for reconfigurable computing

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CODES+ISSS '04: Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Pages 116 - 121

https://doi.org/10.1145/1016720.1016751

Published: 08 September 2004 Publication History

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Abstract

In this paper, we explore the system-level power-performance trade-offs available when implementing streaming embedded applications on fine-grained reconfigurable architectures. We show that an efficient hardware-software partitioning algorithm is required when targeting low-power. However, if the application objective is performance, then we propose the use of dynamically reconfigurable architectures. This work presents a configuration-aware data size partitioning approach. We propose a design methodology that adapts the architecture and used algorithms to the application requirements. The methodology has been proven to work on a real research platform based on Xilinx devices. Finally, we have applied our methodology and algorithms to the case study of image sharpening, which is required nowadays in digital cameras and mobile phones.

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Cited By

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Zompakis NCatthoor FSoudris D(2016)Efficient Configurations for Dynamic Applications in Next Generation Mobile SystemsHandbook of Research on Next Generation Mobile Communication Systems10.4018/978-1-4666-8732-5.ch006(112-147)Online publication date: 2016
https://doi.org/10.4018/978-1-4666-8732-5.ch006
Wang GStitt GLam HGeorge A(2016)Core-level modeling and frequency prediction for DSP applications on FPGAsInternational Journal of Reconfigurable Computing10.1155/2015/7846722015(7-7)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1155/2015/784672
Hsieh JChang YLee W(2011)An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAsProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950944(661-667)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950944
Show More Cited By

Index Terms

Power-performance trade-offs for reconfigurable computing
1. Computer systems organization
  1. Architectures
    1. Other architectures

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Published In

CODES+ISSS '04: Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

September 2004

266 pages

ISBN:158113 9373

DOI:10.1145/1016720

General Chairs:
Alex Orailoglu
University of California, San Diego, CA
,
Pai H. Chou
University of California, Irvine, CA
,
Program Chairs:
Petru Eles
Linköping University, Sweden
,
Axel Jantsch
Royal Institute of Technology, Sweden

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 08 September 2004

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CODES/ISSS04

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CODES/ISSS04: Second IEEE/ACM/IFIP International CODES/ ISSS 2004 Merged Conference

September 8 - 10, 2004

Stockholm, Sweden

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Overall Acceptance Rate 280 of 864 submissions, 32%

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Cited By

View all

Zompakis NCatthoor FSoudris D(2016)Efficient Configurations for Dynamic Applications in Next Generation Mobile SystemsHandbook of Research on Next Generation Mobile Communication Systems10.4018/978-1-4666-8732-5.ch006(112-147)Online publication date: 2016
https://doi.org/10.4018/978-1-4666-8732-5.ch006
Wang GStitt GLam HGeorge A(2016)Core-level modeling and frequency prediction for DSP applications on FPGAsInternational Journal of Reconfigurable Computing10.1155/2015/7846722015(7-7)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1155/2015/784672
Hsieh JChang YLee W(2011)An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAsProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950944(661-667)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950944
Hsieh JChang YLee W(2011)An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAs16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)10.1109/ASPDAC.2011.5722270(661-667)Online publication date: Jan-2011
https://doi.org/10.1109/ASPDAC.2011.5722270
Jówiak LNedjah NFigueroa M(2010)Modern development methods and tools for embedded reconfigurable systemsIntegration, the VLSI Journal10.1016/j.vlsi.2009.06.00243:1(1-33)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1016/j.vlsi.2009.06.002
Banerjee SBozorgzadeh EDutt N(2009)Exploiting application data-parallelism on dynamically reconfigurable architecturesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200349017:2(234-247)Online publication date: 1-Feb-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2003490
Sabhanatarajan KGordon-Ross AOden MNavada MGeorge A(2008)Smart-NICsProceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2008.60(75-80)Online publication date: 7-Apr-2008
https://dl.acm.org/doi/10.1109/ISVLSI.2008.60
Roman SMecha HMozos DSeptien J(2008)Constant complexity scheduling for hardware multitasking in two dimensional reconfigurable field-programmable gate arraysIET Computers & Digital Techniques10.1049/iet-cdt:200700602:6(401)Online publication date: 2008
https://doi.org/10.1049/iet-cdt:20070060
Banerjee SBozorgzadeh EDutt NHirose F(2006)PARLGRANProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118419(491-496)Online publication date: 24-Jan-2006
https://dl.acm.org/doi/10.1145/1118299.1118419
Banerjee SBozorgzadeh EDutt N(2006)Integrating physical constraints in HW-SW partitioning for architectures with partial dynamic reconfigurationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2006.88641114:11(1189-1202)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/TVLSI.2006.886411
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Power-Performance Trade-Offs for Reconfigurable Computing

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