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PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures

Published: 24 January 2006 Publication History

Abstract

Partial dynamic reconfiguration, often called RTR (run-time reconfiguration) is a key feature in modern reconfigurable platforms. While partial RTR enables additional application performance, it imposes physical constraints necessitating simultaneous scheduling and placement while mapping application task graphs onto such architectures. In this paper we present PARLGRAN, an approach that maximizes performance of application task chains by selecting a suitable granularity of data-parallelism for individual data parallel tasks. Our approach focusses on reconfiguration delay overhead and placement-related issues (such as fragmentation) while selecting individual data-parallelism granularity as an integral part of simultaneous scheduling and placement. We demonstrate that our heuristic generates high-quality schedules on an extensive set of over a 1000 synthetic experiments by comparing the results with an approach that tries to statically maximize data-parallelism, i.e., does not consider the overheads and constraints associated with partial RTR. A detailed case-study on JPEG encoding additionally confirms that blindly maximizing data-parallelism can result in schedules even worse than that generated by a simple (but RTR-aware) approach oblivious to data-parallelism.

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Cited By

View all
  • (2016)Resource-Efficient Scheduling for Partially-Reconfigurable FPGA-Based Systems2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW.2016.176(189-197)Online publication date: May-2016
  • (2015)A multiobjective reconfiguration-aware scheduler for FPGA-based heterogeneous architectures2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)10.1109/ReConFig.2015.7393328(1-6)Online publication date: Dec-2015
  • (2014)PaRA-SchedProceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops10.1109/IPDPSW.2014.32(243-250)Online publication date: 19-May-2014
  • Show More Cited By

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Information & Contributors

Information

Published In

cover image ACM Conferences
ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference
January 2006
998 pages
ISBN:0780394518

Sponsors

  • IEEE Circuits and Systems Society
  • SIGDA: ACM Special Interest Group on Design Automation
  • IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
  • IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

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IEEE Press

Publication History

Published: 24 January 2006

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Author Tags

  1. data-parallelism
  2. granularity selection
  3. linear placement
  4. partial dynamic reconfiguration
  5. scheduling

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

View all
  • (2016)Resource-Efficient Scheduling for Partially-Reconfigurable FPGA-Based Systems2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW.2016.176(189-197)Online publication date: May-2016
  • (2015)A multiobjective reconfiguration-aware scheduler for FPGA-based heterogeneous architectures2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)10.1109/ReConFig.2015.7393328(1-6)Online publication date: Dec-2015
  • (2014)PaRA-SchedProceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops10.1109/IPDPSW.2014.32(243-250)Online publication date: 19-May-2014
  • (2014)A transparent and adaptive reconfigurable systemMicroprocessors & Microsystems10.1016/j.micpro.2014.03.00438:5(509-524)Online publication date: 1-Jul-2014
  • (2010)Bandwidth Management in Application Mapping for Dynamically Reconfigurable ArchitecturesACM Transactions on Reconfigurable Technology and Systems10.1145/1839480.18394883:3(1-30)Online publication date: 1-Sep-2010
  • (2010)Modern development methods and tools for embedded reconfigurable systemsIntegration, the VLSI Journal10.1016/j.vlsi.2009.06.00243:1(1-33)Online publication date: 1-Jan-2010
  • (2009)ReferencesReconfigurable System Design and Verification10.1201/9781420062670.bmatt(225-244)Online publication date: 10-Nov-2009
  • (2009)Optimal Loop Unrolling and Shifting for Reconfigurable ArchitecturesACM Transactions on Reconfigurable Technology and Systems10.1145/1575779.15757852:4(1-24)Online publication date: 1-Sep-2009
  • (2009)Task graph scheduling for reconfigurable architectures driven by reconfigurations hiding and resources reuseProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531552(21-26)Online publication date: 10-May-2009
  • (2009)Partitioning and scheduling of task graphs on partially dynamically reconfigurable FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.201573928:5(662-675)Online publication date: 1-May-2009
  • Show More Cited By

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