Article

Low power gate-level design with mixed-V_th (MVT) techniques

Authors:

Frank Grassert,

Dirk TimmermannAuthors Info & Claims

SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design

Pages 278 - 282

https://doi.org/10.1145/1016568.1016641

Published: 04 September 2004 Publication History

Abstract

The reduction of leakage power has become an important issue for high performance designs. One way to achieve low-leakage and high performance designs is the use of multi-threshold techniques. In this paper, a new mixed-V_th (MVT) CMOS design technique is proposed, which uses different threshold voltages within a logic gate. This new technique allows the reduction of leakage power, while the performance stays constant. A set of algorithms is given assigning optimal distribution of gates. Results indicate that the new MVT approach can provide up to 40% leakage reduction by constant performance compared to dual-V_th (DVT) gate-level techniques.

References

[1]

N.S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J.S. Hu, M.J. Irwin, M. Kandemir, and V. Narayanan, Leakage Current: Moore's Law Meets Static Power, in IEEE Computer, p. 68, no. 12 (2003).

Digital Library

[2]

J.K. Kao and A. Chandrakasan, Dual-Threshold Voltage Techniques for Low-Power Digital Circuits, in IEEE Journal of Solid State Circuits, p. 1009, no. 35 (2000).

[3]

M. Hansen, H. Yalcin, and J. P. Hayes, Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering, in IEEE Design and Test, p. 72, no. 16 (1999).

Digital Library

[4]

T. Sakurai and A. Newton, Alpha-Power Law MOSFET Model and its Application to CMOS Inverter Delay and other Formulas, in IEEE Journal of Solid-State Circuits, pp. 584--594, no. 2 (1990).

[5]

N. Sirisantana and K. Roy, Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses, in IEEE Design and Test of computers, pp. 56--63, no. 1 (2004).

Digital Library

[6]

L.Wei, Z. Chen, K. Roy, M. Johnson, Y. Ye, and V.K. De, Design and Optimization of Dual-Threshold Circuits for Low-Voltage Low-Power Applications, in IEEE Trans. on VLSI Systems, pp.16, no. 1 (1999).

Digital Library

[7]

W.Chen, W.Hang, P.Kudva, G.D. Gristede, S.Kosonocky and R.V.Joshi, Mixed Multi-Threshold Differential Cascode Voltage Switch (MT-DCVS) Circuit Styles and Strategies for Low Power VLSI Design, ISLPED'01, California, USA (2001).

Digital Library

[8]

T.Karnik, Y. Ye, J. Tschanz, L. Wei, S. Burns, V. Govindarajulu, V. De, and S. Borkar, Total Power Optimization by Simultaneous Dual-Vt Allocation and Device Sizing in High Performance Microprocessors, in Proceedings of the 39th conference on Design automation, New Orleans, Louisiana (2002).

Digital Library

[9]

V.Sundararajan and K.Parhi, Low Power Synthesis of Dual Threshold Voltage CMOS VLSI Circuits, in Proceedings of the IEEE International Symposium on Low Power Electronics and Design, pp. 139--144 (1999).

Digital Library

[10]

L.Wei, Z.Chen, and K.Roy, Mixed-vth (MVT) CMOS Circuit Design Methodology for Low Power Applications, in Proceedings of the 36th Design Automation Conference, pp. 430--435 (1999).

Digital Library

[11]

L.Wei, K. Roy, and V.De, Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs, in Proceedings of the 13th Int. Conference on VLSI Design, pp. 24--29 (2000).

Digital Library

[12]

L.Wei, K. Roy, and C. Koh, Power Minimization by Simultanous Dual-Vth Assignment and Gate-sizing, in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 413--416 (2000).

[13]

M. Anis and M. Elmasry, in Multi-Threshold CMOS Digital Circuits, Kluwer Academic Publishers (2003).

[14]

H. Veendrick, in Deep-Submicron CMOS ICs, Kluwer Academic Publishers (2000).

[15]

Berkeley Predictive Technology Model, www-device.eecs.berkeley.edu/~ptm (2002).

[16]

United Microelectronics Cooperation, www.umc.com <http://www.umc.com>

[17]

Taiwan Semiconductor Manufacturing Company Ltd., www.tsmc.com

Cited By

Gebregiorgis ATahoori M(2018)Fine-Grained Energy-Constrained Microprocessor Pipeline DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.276754326:3(457-469)Online publication date: 1-Mar-2018
https://dl.acm.org/doi/10.1109/TVLSI.2017.2767543
Alma'aitah AAbid Z(2011)Transistor level optimization of sub-pipelined AES design in CMOS 65nmICM 2011 Proceeding10.1109/ICM.2011.6177419(1-4)Online publication date: Dec-2011
https://doi.org/10.1109/ICM.2011.6177419
Mande SChandorkar SChandorkar A(2011)Process variation aware dual-Vth assignment technique for low power nanoscale CMOS designMicroelectronics Reliability10.1016/j.microrel.2011.04.01151:12(2357-2365)Online publication date: Dec-2011
https://doi.org/10.1016/j.microrel.2011.04.011
Show More Cited By

Index Terms

Low power gate-level design with mixed-V_th (MVT) techniques
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

Recommendations

Total leakage power optimization with improved mixed gates
SBCCI '05: Proceedings of the 18th annual symposium on Integrated circuits and system design

Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness of gate oxide layer Tox. In this paper, we propose a new method that ...
Impact of channel length, gate insulator thickness, gate insulator material, and temperature on the performance of nanoscale FETs

Aggressive technology scaling as per Moore's law has led to elevated power dissipation levels owing to an exponential increase in subthreshold leakage power. Short channel effects (SCEs) due to channel length reduction, gate insulator thickness change, ...
Dual-material double-gate tunnel FET: gate threshold voltage modeling and extraction

A new analytical model for the gate threshold voltage ($$V_\mathrm{TG}$$VTG) of a dual-material double-gate (DMDG) tunnel field-effect transistor (TFET) is reported. The model is derived by solving the quasi-two-dimensional Poisson's equation in the ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

SBCCI '04: Proceedings of the 17th symposium on Integrated circuits and system design

September 2004

296 pages

ISBN:1581139470

DOI:10.1145/1016568

General Chair:
Edna Natividade da Silva Barros
Federal University of Pernambuco, Brazil
,
Program Chairs:
Flàvio Rech Wagner
Federal University of Rio Grande do Sul, Brazil
,
Luigi Carro
Federal University of Rio Grande do Sul, Brazil
,
Franz Josef Rammig
University of Paderborn, Germany

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 04 September 2004

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

SBCCI04

Sponsor:

SBCCI04: 17th Symposium on Integrated Circuits and System Design

September 7 - 11, 2004

Pernambuco, Brazil

Acceptance Rates

Overall Acceptance Rate 133 of 347 submissions, 38%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

11
Total Citations
View Citations
404
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)0

Reflects downloads up to 16 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

Gebregiorgis ATahoori M(2018)Fine-Grained Energy-Constrained Microprocessor Pipeline DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.276754326:3(457-469)Online publication date: 1-Mar-2018
https://dl.acm.org/doi/10.1109/TVLSI.2017.2767543
Alma'aitah AAbid Z(2011)Transistor level optimization of sub-pipelined AES design in CMOS 65nmICM 2011 Proceeding10.1109/ICM.2011.6177419(1-4)Online publication date: Dec-2011
https://doi.org/10.1109/ICM.2011.6177419
Mande SChandorkar SChandorkar A(2011)Process variation aware dual-Vth assignment technique for low power nanoscale CMOS designMicroelectronics Reliability10.1016/j.microrel.2011.04.01151:12(2357-2365)Online publication date: Dec-2011
https://doi.org/10.1016/j.microrel.2011.04.011
Sun YXiao LLiu Y(2010)Ground bounce reduction in power gating circuits using input vector control2010 Academic Symposium on Optoelectronics and Microelectronics Technology and 10th Chinese-Russian Symposium on Laser Physics and Laser TechnologyOptoelectronics Technology (ASOT)10.1109/RCSLPLT.2010.5615310(345-348)Online publication date: Jul-2010
https://doi.org/10.1109/RCSLPLT.2010.5615310
Nagarajan CYuan LQu GStamps B(2009)Leakage optimization using transistor-level dual threshold voltage cell libraryProceedings of the 2009 10th International Symposium on Quality of Electronic Design10.1109/ISQED.2009.4810270(62-67)Online publication date: 16-Mar-2009
https://dl.acm.org/doi/10.1109/ISQED.2009.4810270
Salomon RSill F(2007)High-speed, low-leakage integrated circuitsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2006.10.00153:5-6(321-327)Online publication date: 1-May-2007
https://dl.acm.org/doi/10.1016/j.sysarc.2006.10.001
Engel KKalinowski TLabahn RSill FTimmermann D(2006)Algorithms for Leakage Reduction with Dual Threshold Design Techniques2006 International Symposium on System-on-Chip10.1109/ISSOC.2006.321980(1-4)Online publication date: Nov-2006
https://doi.org/10.1109/ISSOC.2006.321980
Sill FSalomon R(2006)Evolving High-Speed, Energy-Efficient Integrated Circuits2006 IEEE International Conference on Evolutionary Computation10.1109/CEC.2006.1688704(3121-3128)Online publication date: 2006
https://doi.org/10.1109/CEC.2006.1688704
Salomon RSill F(2006)Biologically-Inspired optimization of circuit performance and leakageProceedings of the 19th international conference on Architecture of Computing Systems10.1007/11682127_25(352-366)Online publication date: 13-Mar-2006
https://dl.acm.org/doi/10.1007/11682127_25
Sill FGrassert FTimmermann DGalup-Montoro CBampi SOrailoglu A(2005)Total leakage power optimization with improved mixed gatesProceedings of the 18th annual symposium on Integrated circuits and system design10.1145/1081081.1081123(154-159)Online publication date: 4-Sep-2005
https://dl.acm.org/doi/10.1145/1081081.1081123
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten