Article

A low-power bus design using joint repeater insertion and coding

Authors:

Srinivasa R. Sridhara,

Naresh R. ShanbhagAuthors Info & Claims

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

Pages 99 - 102

https://doi.org/10.1145/1077603.1077629

Published: 08 August 2005 Publication History

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Abstract

In this paper, we propose joint repeater insertion and crosstalk avoidance coding as a low-power alternative to repeater insertion for global bus design in nanometer technologies. We develop a methodology to calculate the repeater size and separation that minimize the total power dissipation for joint repeater insertion and coding for a specific delay target. This methodology is employed to obtain power vs. delay trade-offs for 130-nm, 90-nm, 65-nm, and 45-nm technology nodes. Using ITRS technology scaling data, we show that proposed technique provides 54%, 67%, and 69% power savings over optimally repeater-inserted 10-mm 32-bit bus at 90-nm, 65-nm, and 45-nm technology nodes, respectively, while achieving the same delay

References

[1]

International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2003. {Online}. Available: http://public.itrs.net

Google Scholar

[2]

V. Soteriou and L.-S. Peh, "Design-space exploration of power-aware on/off interconnection networks," in Proc. ICCD, 2004, pp. 510--517.

Digital Library

Google Scholar

[3]

L. Benini and G. D. Micheli, "Networks on chips: a new SoC paradigm," IEEE Computer, vol. 35, pp. 70--78, Jan. 2002.

Digital Library

Google Scholar

[4]

H. Bakoglu, Circuits, Interconnects and Packing for VLSI. Reading, MA: Addison-Wesley, 1990.

Google Scholar

[5]

K. Banerjee and A. Mehrotra, "A power-optimal repeater insertion methodology for global interconnects in nanometer designs," IEEE Trans. Electron Devices, vol. 49, pp. 2001--2007, Nov. 2002.

Crossref

Google Scholar

[6]

P. P. Sotiriadis and A. Chandrakasan, "Reducing bus delay in submicron technology using coding," in Proc. ASP-DAC, 2001, pp. 109--114.

Digital Library

Google Scholar

[7]

C. Duan, A. Tirumala, and S. P. Khatri, "Analysis and avoidance of cross-talk in on-chip buses," in Proc. Hot Interconnects, 2001, pp. 133--138.

Digital Library

Google Scholar

[8]

B. Victor and K. Keutzer, "Bus encoding to prevent crosstalk delay," in Proc. ICCAD, 2001, pp. 57--63.

Digital Library

Google Scholar

[9]

S. R. Sridhara, A. Ahmed, and N. R. Shanbhag, "Area and energy-efficient crosstalk avoidance codes for on-chip buses," in Proc. ICCD, 2004, pp. 12--17.

Digital Library

Google Scholar

[10]

S. R. Sridhara and N. R. Shanbhag, "Coding for reliable on-chip buses: fundamental limits and practical codes," in Proc. VLSI Design, 2005, pp. 417--422.

Digital Library

Google Scholar

[11]

M. L. Mui, K. Banerjee, and A. Mehrotra, "A global interconnect optimization scheme for nanometer scale vlsi with implications for latency, bandwidth, and power dissipation," IEEE Trans. Electron Devices, vol. 51, pp. 195--203, Feb. 2004.

Crossref

Google Scholar

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Rao JRao P(2012)Design and implementation of efficient CODECs for on-chip buses to reduce both crosstalk delay and power dissipation2012 NATIONAL CONFERENCE ON COMPUTING AND COMMUNICATION SYSTEMS10.1109/NCCCS.2012.6413016(1-5)Online publication date: Nov-2012
https://doi.org/10.1109/NCCCS.2012.6413016
Pasricha SDutt N(2008)Encoding Techniques for On-Chip Communication ArchitecturesOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00007-4(253-300)Online publication date: 2008
https://doi.org/10.1016/B978-0-12-373892-9.00007-4
Sainarayanan KRaghunandan CSrinivas M(2007)Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding SchemeProceedings of the IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2007.35(401-408)Online publication date: 9-Mar-2007
https://dl.acm.org/doi/10.1109/ISVLSI.2007.35

Index Terms

A low-power bus design using joint repeater insertion and coding
1. Hardware
  1. Integrated circuits
    1. Interconnect

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Published In

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

August 2005

400 pages

ISBN:1595931376

DOI:10.1145/1077603

General Chairs:
Kaushik Roy
Purdue University
,
Vivek Tiwari
Intel

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 08 August 2005

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August 8 - 10, 2005

CA, San Diego, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Rao JRao P(2012)Design and implementation of efficient CODECs for on-chip buses to reduce both crosstalk delay and power dissipation2012 NATIONAL CONFERENCE ON COMPUTING AND COMMUNICATION SYSTEMS10.1109/NCCCS.2012.6413016(1-5)Online publication date: Nov-2012
https://doi.org/10.1109/NCCCS.2012.6413016
Pasricha SDutt N(2008)Encoding Techniques for On-Chip Communication ArchitecturesOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00007-4(253-300)Online publication date: 2008
https://doi.org/10.1016/B978-0-12-373892-9.00007-4
Sainarayanan KRaghunandan CSrinivas M(2007)Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding SchemeProceedings of the IEEE Computer Society Annual Symposium on VLSI10.1109/ISVLSI.2007.35(401-408)Online publication date: 9-Mar-2007
https://dl.acm.org/doi/10.1109/ISVLSI.2007.35

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Edge effect aware low-power crosstalk avoidance technique for 3D integration

An analysis of interconnect delay minimization by low-voltage repeater insertion

Efficient interconnect design with novel repeater insertion for low power applications

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