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Reducing bus delay in submicron technology using coding

Published: 30 January 2001 Publication History

Abstract

In this paper we study the delay associated with transmission of data through busses. Previous work in this area has presented models for delay assuming a distributed model or a lumped capacitive coupling between wires. In this paper we extend the Elmore delay to account for a distributed model with distributed coupling component and an arbitrary number of lines driven by independent sources. The effect of data patterns is taken into account allowing us to estimate the delay on a sample by sample basis instead of making a worst case assumption. Using this detailed wire delay model, we propose a technique to speed up the communication through a data bus using coding. The idea is to encode the data being transmitted through the bus with the goal of eliminating certain types of transitions that require a large delay. We show that by using proper encoding techniques, the bus can be sped up by a factor of 2.

References

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  • (2022)Learning-Based On-Chip Parallel Interconnect Delay Estimation2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)10.1109/MOCAST54814.2022.9837716(1-6)Online publication date: 8-Jun-2022
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cover image ACM Conferences
ASP-DAC '01: Proceedings of the 2001 Asia and South Pacific Design Automation Conference
January 2001
662 pages
ISBN:0780366344
DOI:10.1145/370155
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 30 January 2001

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ASP-DAC01
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  • IPSJ
  • SIGDA
  • IEEE HK CAS

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Cited By

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  • (2025)JoBiS: Joint capacitance and inductance bit stuffing CAC for interposer based multi-chip Deep Learning AcceleratorIntegration10.1016/j.vlsi.2025.102347(102347)Online publication date: Feb-2025
  • (2024)Combinatorial constructions of optimal low-power error-correcting cooling codesDesigns, Codes and Cryptography10.1007/s10623-024-01391-092:8(2235-2252)Online publication date: 4-Apr-2024
  • (2022)Learning-Based On-Chip Parallel Interconnect Delay Estimation2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)10.1109/MOCAST54814.2022.9837716(1-6)Online publication date: 8-Jun-2022
  • (2021)ST-CAC: a low-cost crosstalk avoidance coding mechanism based on three-valued numerical systemThe Journal of Supercomputing10.1007/s11227-020-03527-077:7(6692-6713)Online publication date: 2-Jan-2021
  • (2021)Transition Based Odd/Full Invert Coding Scheme for Crosstalk Avoidance and Low Power Consumption in NoC LinksAdvances in Signal and Data Processing10.1007/978-981-15-8391-9_21(279-298)Online publication date: 12-Jan-2021
  • (2018)Misalignment-aware delay modeling of narrow on-chip interconnects considering variability2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST)10.1109/MOCAST.2018.8376593(1-4)Online publication date: May-2018
  • (2018)Models for Determining the Influence of DFSimulation and Optimization of Digital Circuits10.1007/978-3-319-71637-4_3(137-211)Online publication date: 13-Apr-2018
  • (2018)General Issues of Gate-Level Simulation and Optimization of Digital Circuits with Consideration of Destabilizing FactorsSimulation and Optimization of Digital Circuits10.1007/978-3-319-71637-4_1(1-75)Online publication date: 13-Apr-2018
  • (2015)Addressing NoC Reliability Through an Efficient Fibonacci-Based Crosstalk Avoidance Codec DesignAlgorithms and Architectures for Parallel Processing10.1007/978-3-319-27137-8_55(756-770)Online publication date: 16-Dec-2015
  • (2012)Coding for jointly optimizing energy and peak current in deep sub-micron VLSI interconnects2012 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2012.6271974(3090-3093)Online publication date: May-2012
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