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Using cache memory to reduce processor-memory traffic

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James R. GoodmanAuthors Info & Claims

ISCA '83: Proceedings of the 10th annual international symposium on Computer architecture

Pages 124 - 131

https://doi.org/10.1145/800046.801647

Published: 13 June 1983 Publication History

Abstract

The importance of reducing processor-memory bandwidth is recognized in two distinct situations: single board computer systems and microprocessors of the future. Cache memory is investigated as a way to reduce the memory-processor traffic. We show that traditional caches which depend heavily on spatial locality (look-ahead) for their performance are inappropriate in these environments because they generate large bursts of bus traffic. A cache exploiting primarily temporal locality (look-behind) is then proposed and demonstrated to be effective in an environment where process switches are infrequent. We argue that such an environment is possible if the traffic to backing store is small enough that many processors can share a common memory and if the cache data consistency problem is solved. We demonstrate that such a cache can indeed reduce traffic to memory greatly, and introduce an elegant solution to the cache coherency problem.

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Index Terms

Using cache memory to reduce processor-memory traffic
1. General and reference
  1. Cross-computing tools and techniques
    1. Performance
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Published In

cover image ACM Conferences

ISCA '83: Proceedings of the 10th annual international symposium on Computer architecture

June 1983

424 pages

ISBN:0897911016

DOI:10.1145/800046

ACM SIGARCH Computer Architecture News Volume 11, Issue 3
June 1983
413 pages
ISSN:0163-5964
DOI:10.1145/1067651
Issue’s Table of Contents

Copyright © 1983 Author.

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SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS: Computer Society

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Association for Computing Machinery

New York, NY, United States

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Published: 13 June 1983

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https://doi.org/10.1109/TPDS.2023.3268662
Frenkel CBol DIndiveri G(2023)Bottom-Up and Top-Down Approaches for the Design of Neuromorphic Processing Systems: Tradeoffs and Synergies Between Natural and Artificial IntelligenceProceedings of the IEEE10.1109/JPROC.2023.3273520111:6(623-652)Online publication date: Jun-2023
https://doi.org/10.1109/JPROC.2023.3273520
Wang CHe KFan RWang XWang WHao Q(2023)CXL over Ethernet: A Novel FPGA-based Memory Disaggregation Design in Data Centers2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM57271.2023.00017(75-82)Online publication date: May-2023
https://doi.org/10.1109/FCCM57271.2023.00017
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