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Defect-Tolerant Mapping of CMOL Circuit Targeting Delay Optimization

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Abstract

In view of the significant number of defective nanodevices in the Cmos/nanowire/MOLecular hybrid (CMOL) circuit, defect-tolerant mapping is an essential step to achieve correct logic operations in defective CMOL circuits. However, less effort has been made to improve circuit delay by defect-tolerant strategies. In this paper, the factors affecting the delay of mapped circuits are analyzed, and the path-tree based defect-tolerant mapping method for the delay optimization is proposed. From the logic-domain, the terminology of the path tree is presented, and the logic circuit is first partitioned into multiple path trees. Then, the mapping areas in the physic-domain are pre-planned for (near) critical path trees. During the mapping process, the specific mapping modes and an updating strategy are formulated to map the path trees: inputs are mapped based on input sorting; (near) critical path trees are mapped with priority, while the others are mapped in a hierarchical way. Finally, an improved tabu search algorithm is employed to verify the validity of the proposed defect-tolerant mapping method. Experimental evaluations on the ISCAS benchmarks show that the proposed method can reduce circuit delay by 15.22%.

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Authors and Affiliations

  1. Faculty of Electrical Engineering and Computer Science, Ningbo University, Ningbo, 315211, China

    Xiao-Jing Zha, Yin-Shui Xia, Shang-Luan Xie & Zhu-Fei Chu

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  1. Xiao-Jing Zha
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  2. Yin-Shui Xia
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  3. Shang-Luan Xie
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  4. Zhu-Fei Chu
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Correspondence to Yin-Shui Xia or Zhu-Fei Chu.

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Zha, XJ., Xia, YS., Xie, SL. et al. Defect-Tolerant Mapping of CMOL Circuit Targeting Delay Optimization. J. Comput. Sci. Technol. 36, 1118–1132 (2021). https://doi.org/10.1007/s11390-021-0904-0

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