article

Nanowire-based programmable architectures

Author:

André DehonAuthors Info & Claims

ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 1, Issue 2

Pages 109 - 162

https://doi.org/10.1145/1084748.1084750

Published: 01 July 2005 Publication History

Abstract

Chemists can now construct wires which are just a few atoms in diameter; these wires can be selectively field-effect gated, and wire crossings can act as diodes with programmable resistance. These new capabilities present both opportunities and challenges for constructing nanoscale computing systems. The tiny feature sizes offer a path to economically scale down to atomic dimensions. However, the associated bottom-up synthesis techniques only produce highly regular structures and come with high defect rates and minimal control during assembly. To exploit these technologies, we develop nanowire-based architectures which can bridge between lithographic and atomic-scale feature sizes and tolerate defective and stochastic assembly of regular arrays to deliver high density universal computing devices. Using 10nm pitch nanowires, these nanowire-based programmable architectures offer one to two orders of magnitude greater mapped-logic density than defect-free lithographic FPGAs at 22nm.

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Index Terms

Nanowire-based programmable architectures
1. Hardware
  1. Emerging technologies
  2. Integrated circuits
    1. Logic circuits
      1. Combinational circuits

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cover image ACM Journal on Emerging Technologies in Computing Systems

ACM Journal on Emerging Technologies in Computing Systems Volume 1, Issue 2

July 2005

90 pages

ISSN:1550-4832

EISSN:1550-4840

DOI:10.1145/1084748

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Copyright © 2005 ACM.

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

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Published: 01 July 2005

Published in JETC Volume 1, Issue 2

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