Abstract
Electronics obtained through the bottom-up approach of molecular-level control of material composition and structure may lead to devices and fabrication strategies not possible with top-down methods. This review presents a brief summary of bottom-up and hybrid bottom-up/top-down strategies for nanoelectronics with an emphasis on memories based on the crossbar motif. First, we will discuss representative electromechanical and resistance-change memory devices based on carbon nanotube and core–shell nanowire structures, respectively. These device structures show robust switching, promising performance metrics and the potential for terabit-scale density. Second, we will review architectures being developed for circuit-level integration, hybrid crossbar/CMOS circuits and array-based systems, including experimental demonstrations of key concepts such lithography-independent, chemically coded stochastic demultipluxers. Finally, bottom-up fabrication approaches, including the opportunity for assembly of three-dimensional, vertically integrated multifunctional circuits, will be critically discussed.
This is a preview of subscription content, access via your institution
Access options
Subscribe to this journal
Receive 12 print issues and online access
$259.00 per year
only $21.58 per issue
Buy this article
- Purchase on SpringerLink
- Instant access to full article PDF
Prices may be subject to local taxes which are calculated during checkout
Similar content being viewed by others
References
International Technology Roadmap for Semiconductors 2005 edn, available online at http://public.itrs.net/.
Frank, D. J. et al. Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE 89, 259–288 (2001).
Likharev, K. K. in Nano and Giga Challenges in Microelectronics (eds Greer, J., Korkin, A. & Labanowski, J.) 27–68 (Elsevier, Amsterdam, 2003).
McEuen, P. L., Fuhrer, M. S. & Park, H. Single-walled carbon nanotube electronics. IEEE Trans. Nanotechnol. 1, 78–85 (2002).
Lieber, C. M. Nanoscale science and technology: building a big future from small things. Mater. Res. Soc. Bull. 28, 486–491 (2003).
Heath, J. R., Kuekes, P. J. Snider, G. S. & Williams, R. S. A defect-tolerant computer architecture: opportunities for nanotechnology. Science 280, 1716–1721 (1998).
Stan, M. R., Franzon, P. D., Goldstein, S. C., Lach, J. C. & Ziegler, M. M. Molecular electronics: from devices and interconnect to circuits and architecture. Proc. IEEE 91, 1940–1957 (2003).
DeHon, A. Array-based architecture for FET-based, nanoscale electronics. IEEE Trans. Nanotechnol. 2, 23–32 (2003).
Cui, Y. & Lieber, C. M. Functional nanoscale electronic devices assembled using silicon nanowire building blocks. Science 291, 851–853 (2001).
Huang, Y. et al. Logic gates and computation from assembled nanowire building blocks. Science 294, 1313–1317 (2001).
Whang, D., Jin, S., Wu, Y. & Lieber, C. M. Large-scale hierarchical organization of nanowire arrays for integrated nanosystems. Nano Lett. 3, 1255–1259 (2003).
Rueckes, T. et al. Carbon nanotube-based nonvolatile random access memory for molecular computing. Science 289, 94–97 (2000).
Collier, C. P. et al. Electronically configurable molecular-based logic gates. Science 285, 391–394 (1999).
Chen, Y. et al. Nanoscale molecular-switch crossbar circuits. Nanotechnology 14, 462–468 (2003).
Duan, X. F., Huang, Y. & Lieber, C. M. Nonvolatile memory and programmable logic from molecule-gated nanowires. Nano Lett. 2, 487–490 (2002).
Zankovych, S., Hoffmann, T., Seekamp, J., Bruch, J. U. & Torres, C. M. S. Nanoimprint lithography: challenges and prospects. Nanotechnology 12, 91–95 (2001).
Chou, S. Y., Krauss, P. R. & Renstrom, P. J. Imprint lithography with 25-nanometer resolution. Science 272, 85–87 (1996).
Melosh, N. A. et al. Ultrahigh-density nanowire lattices and circuits. Science 300, 112–115 (2003).
Brueck, S. R. J. in International Trends in Applied Optics (eds Guenther, A. H. & Holst, G. C.) 85–110 (SPIE, Bellingham, Washington, 2002).
Zhong, Z., Wang, D., Cui, Y., Bockrath, M. W. & Lieber, C. M. Nanowire crossbar arrays as address decoders for integrated nanosystems. Science 302, 1377–1379 (2003).
Strukov, D. B. & Likharev, K. K. CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices. Nanotechnology 16, 888–900 (2005).
Strukov, D. B. & Likharev, K. K. Prospects for terabit-scale nanoelectronic memories. Nanotechnology 16, 137–148 (2005).
Snider, G. S. & Williams, R. S. Nano/CMOS architectures using a field-programmable nanowire interconnect. Nanotechnology 18, 035204 (2007).
Snider, G. S. Computing with hysteretic resistor crossbars. Appl. Phys. A. 80, 1165–1172 (2005).
Kuekes, P. J., Stewart, D. R. & Williams, R. S. The crossbar latch: logic value storage, restoration, and inversion in crossbar circuits. J. Appl. Phys. 97, 034301 (2003).
Reed, M. A., Zhou, C., Muller, C. J., Burgin, T. P. & Tour, J. M. Conductance of a molecular junction. Science 278, 252–254 (1997).
Reed, M. A., Chen, J., Rawlett, A. M., Price, D. W. & Tour, J. M. Molecular random access memory cell. Appl. Phys. Lett. 78, 3735–3737 (2001).
Donhauser, Z. J. et al. Conductance switching in single molecules through conformational changes. Science 292, 2303–2307 (2001).
Lau, C. N., Stewart, D. R., Williams, R. S. & Bockrath, M. Direct observation of nanoscale switching centers in metal/molecule/metal structures. Nano Lett. 4, 569–572 (2004).
Collier, C. P. et al. A [2]catenane-based solid state electronically reconfigurable switch. Science 289, 1172–1175 (2000).
Green, J. E. et al. A 160-kilobit molecular electronic memory patterned at 1011 bits per square centimetre. Nature 445, 414–417 (2007).
Seminario, J. M., Zacarias, A. G. & Tour, J. M. Theoretical study of a molecular resonant tunneling diode. J. Am. Chem. Soc. 122, 3015–3020 (2000).
Di Ventra, M., Pantelides, S. T. & Lang, N. D. First-principles calculation of transport properties of a molecular device. Phys. Rev. Lett. 84, 979–982 (2000).
Chen, J. et al. Room-temperature negative differential resistance in nanoscale molecular junctions. Appl. Phys. Lett. 77, 1224–1226 (2000).
Flood, A. H., Stoddart, J. F., Steuerman, D. W. & Heath, J. R. Whence molecular electronics? Science 306, 2055–2056 (2004).
Waser, R. & Aono, M. Nanoionics-based resistive switching memories. Nature Mater. 6, 833–840 (2007).
Nantero; http://www.nantero.com/index.html.
Owen, A. E., Lecomber, P. G., Hajto, J., Rose, M. J. & Snell, A. Switching in amorphous devices. Int. J. Electron. 73, 897–906 (1992).
Jafar, M. & Haneman, D. Switching in amorphous-silicon devices. Phys. Rev. B 49, 13611–13615 (1994).
Scott, J. C. Is there an immortal memory? Science 304, 62 (2004).
Kuekes, P. J., Robinett, W. & Williams, R. S. Improved voltage margins using linear error-correcting codes in resistor-logic demultiplexers for nanoelectronics. Nanotechnology 16, 1419–1432 (2005).
Hu, J., Branz, H. M., Crandall, R. S., Ward, S. & Wang, Q. Switching and filament formation in hot-wire CVD p-type a-Si:H devices. Thin Solid Films 430, 249–252 (2003).
Avila, A. & Asomoza, R. Switching in coplanar amorphous hydrogenated silicon devices. Solid State Electron. 44, 17–27 (2000).
Goronkin, H. & Yang, Y. High-performance emerging solid-state memory technologies. Mater. Res. Soc. Bull. 29, 805–808 (2004).
Wuttig, M. & Yamada, N. Phase-change materials for rewriteable data storage. Nature Mater. 6, 824–832 (2007).
Jung, Y., Lee, S.-H., Ko, D.-K. & Agarwal, R. Synthesis and characterization of Ge2Sb2Te5 nanowires with memory switching effect. J. Am. Chem. Soc 128, 14026–14027 (2006).
Lee, S.-H., Ko, D.-K., Jung, Y. & Agarwal, R. Size-dependent phase transition memory switching behavior and low writing currents in GeTe nanowires. Appl. Phys. Lett. 89, 223116 (2006).
Yu, D., Wu, J., Gu, Q. & Park, H. Germanium telluride nanowires and nanohelices with memory-switching behavior. J. Am. Chem. Soc. 128, 8148–8149 (2006).
Meister, S. et al. Synthesis and characterization of phase-change nanowires. Nano Lett 6, 1514–1517 (2006).
Lankhorst, M. H. R., Ketelaars, B. W. S. M. M. & Wolters, R. A. M. Low-cost and nanoscale non-volatile memory concept for future silicon chips. Nature Mater. 4, 347–352 (2005).
Chen, Z. et al. An integrated logic circuit assembled on a single carbon nanotube. Science 311, 1735 (2006).
DeHon, A., Lincoln, P. & Savage, J. E. Stochastic assembly of sublithographic nanoscale interfaces. IEEE Trans. Nanotechnol. 2, 165–174 (2003).
Huang, Y., Duan, X. F., Wei, Q. Q. & Lieber, C. M. Directed assembly of one-dimensional nanostructures into functional networks. Science 291, 630–633 (2001).
Yang, C., Zhong, Z. & Lieber, C. M. Encoding electronic properties by synthesis of axial modulation-doped silicon nanowires. Science 310, 1304–1307 (2005).
Kuekes, P. J. et al. Resistor-logic demultiplexers for nanoelectronics based on constant-weight codes. Nanotechnology 17, 1052–1061 (2006).
Likharev, K. K. & Strukov, D. B. in Introducing Molecular Electronics (eds Cuniberti, G., Fagas, G. & Richter, K.) 447–477 (Springer, Berlin, 2005).
Jin, S. et al. Scalable interconnection and integration of nanowire devices without registration. Nano Lett. 4, 915–919 (2004).
Jung, G. Y. et al. Fabrication of multi-bit crossbar circuits at sub-50 nm half-pitch by using UV-based nanoimprint lithography. J. Photopolym. Sci. Technol. 18, 565–570 (2005).
Javey, A., Nam, S. W., Friedman, R. S., Yan, H. & Lieber, C. M. Layer-by-layer assembly of nanowires for three-dimensional, multifunctional electronics. Nano Lett. 7, 773–777 (2007).
Patolsky, F. et al. Detection, stimulation, and inhibition of neuronal signals with high-density nanowire transistor arrays. Science 313, 100–104 (2006).
Acknowledgements
We thank many of our colleagues at the University of Michigan and Harvard University, particularly T. Rueckes, Y. Dong, G. Yu, Y. Chen, Z. Zhong, X. Duan, Y. Huang and S. Y. Jo for assistance, and A. DeHon and P. Lincoln for critical discussions. W.L. acknowledges support by the National Science Foundation (CCF-0621823). C.M.L. acknowledges support by Air Force Office of Scientific Research, Defense Advanced Research Projects Agency, Intel, and Samsung Electronics.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Lu, W., Lieber, C. Nanoelectronics from the bottom up. Nature Mater 6, 841–850 (2007). https://doi.org/10.1038/nmat2028
Issue Date:
DOI: https://doi.org/10.1038/nmat2028