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21st ETS 2016: Amsterdam, Netherlands
- 21th IEEE European Test Symposium, ETS 2016, Amsterdam, Netherlands, May 23-27, 2016. IEEE 2016, ISBN 978-1-4673-9659-2
- Said Hamdioui, Giorgio Di Natale, Bram Kruseman, Maria K. Michael, Haralampos-G. D. Stratigopoulos:
ETS 2016 foreword. 1 - Hans-Joachim Wunderlich, Peter C. Maxwell:
ETS 2015 best paper. 1 - Lars Reger:
Securely connected vehicles - what it takes to make self-driving cars a reality. 1 - Jing Zhang, Lars-Johan Fritz, Liang Liu
, Erik Larsson
Compressor design for silicon debug. 1-2 - Tasuku Fujibe, Kazuki Shirahata, Takeshi Mizushima, Hidenobu Matsumura, Daisuke Watanabe, Hiroyuki Mineo, Shin Masuda:
An optical/electrical test system for 100Gb/s optical interconnection devices with high volume testing capability. 1-2 - Satish Grandhi, Elsa Dupraz, Christian Spagnol, Valentin Savin
CPE: Codeword Prediction Encoder. 1-2 - Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue:
Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC. 1-2 - Nasim Pour Aryan, Christian Funke, Jens Bargfrede, Cenk Yilmaz, Doris Schmitt-Landsiedel, Georg Georgakos:
In situ measurement of aging-induced performance degradation in digital circuits. 1-2 - Ithihasa Reddy Nirmala, Deepak Vontela, Swaroop Ghosh, Anirudh Iyengar:
A novel threshold voltage defined switch for circuit camouflaging. 1-2 - Varadan Savulimedu Veeravalli, Andreas Steininger
Study of a delayed single-event effect in the Muller C-element. 1-2 - Farrokh Ghani Zadegan
A self-reconfiguring IEEE 1687 network for fault monitoring. 1-6 - Amir Charif, Nacer-Eddine Zergainoh, Michael Nicolaidis:
Addressing transient routing errors in fault-tolerant Networks-on-Chips. 1-6 - Michael A. Kochte, Rafal Baranowski, Matthias Sauer, Bernd Becker
Formal verification of secure reconfigurable scan network infrastructure. 1-6 - Shaofu Yang, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Testing of small delay faults in a clock network. 1-6 - Abhishek Koneru, Krishnendu Chakrabarty
Analysis of electrostatic coupling in monolithic 3D integrated circuits and its impact on delay testing. 1-6 - Han-Yu Wu, Yong-Xiao Chen, Jin-Fu Li:
A built-in method for measuring the delay of TSVs in 3D ICs. 1-6 - Riccardo Cantoro
On the diagnostic analysis of IEEE 1687 networks. 1-2 - Artur Jutman
On coverage of timing related faults at board level. 1-2 - Imran Wali, Bastien Deveautour, Arnaud Virazel
A low-cost susceptibility analysis methodology to selectively harden logic circuits. 1-2 - Te-Hui Chen, David C. Keezer
A 40Gbps economic extension board and FPGA-based testing platform. 1-2 - Weida Chen, Yongxin Zhu, Xinyi Liu, Xinyang Li, Dongyu Ou:
Combining the histogram method and the ultrafast segmented model identification of linearity errors algorithm for ADC linearity testing. 1-2 - Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara:
A scheduling method for hierarchical testability based on test environment generation results. 1-2 - Illani Mohd Nawi, Basel Halak
The influence of hysteresis voltage on single event transients in a 65nm CMOS high speed comparator. 1-2 - Ahmed Ibrahim
Analysis and design of an on-chip retargeting engine for IEEE 1687 networks. 1-6 - Michele Portolan
A novel test generation and application flow for functional access to IEEE 1687 instruments. 1-6 - Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler
VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers. 1-6 - Cheng-Wen Wu:
Is IoT coming to the rescue of semiconductor? 1 - Francisco Mesalles, Hector Villacorta, Michel Renovell, Víctor H. Champac:
Behavior and test of open-gate defects in FinFET based cells. 1-6 - Jeroen De Coster, Peter De Heyn, Marianna Pantouvaki, Brad Snyder, Hongtao Chen, Erik Jan Marinissen
Test-station for flexible semi-automatic wafer-level silicon photonics testing. 1-6 - Gildas Léger
Questioning the reliability of Monte Carlo simulation for machine learning test validation. 1-6 - Antonio J. Ginés
Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator. 1-6 - Paolo Gai, Massimo Violante:
Automotive embedded software architecture in the multi-core age. 1-8 - Jean Durupt, Pascal Vivet
IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system. 1-6 - Ran Wang, Krishnendu Chakrabarty
A design-for-test solution for monolithic 3D integrated circuits. 1-6 - Panagiotis Georgiou, Fotios Vartziotis
Two-dimensional time-division multiplexing for 3D-SoCs. 1-6 - Peter C. Maxwell, Friedrich Hapke, Huaxing Tang:
Cell-aware diagnosis: Defective inmates exposed in their cells. 1-6 - Sin-Yu Wei, Bing-Yang Lin, Cheng-Wen Wu
A fast sweep-line-based failure pattern extractor for memory diagnosis. 1-6 - Amin Vali, Nicola Nicolici:
Bit-flip detection-driven selection of trace signals. 1-6 - Adit D. Singh:
Cell Aware and stuck-open tests. 1-6 - Salem Abdennadher, Saghir A. Shaikh:
Practices in High-Speed IO testing. 1-8 - Subhasish Mitra:
Cross-layer resilience. 1 - Phil Nigh:
Testing in the year 2024 - big changes are coming. 1 - Stephen Sunter, Alessandro Valerio, Riccardo Miglierina:
Measuring defect tolerance within mixed-signal ICs. 1-2 - Peter Sarson:
Group delay filter measurement using a chirp. 1-2 - Seetal Potluri, Satya Trinadh, Siddhant Saraf, Kamakoti Veezhinathan:
Component fault localization using switching current measurements. 1-2 - Boyang Du, Luca Sterpone
A new EDA flow for the mitigation of SEUs in dynamic reconfigurable FPGAs. 1-2 - Josef Kinseher, Moritz Völker, Leonardo Bonet Zordan, Ilia Polian:
Failure mechanisms and test methods for the SRAM TVC write-assist technique. 1-2 - Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor, Wim Dehaene:
Read path degradation analysis in SRAM. 1-2 - Niels Thole, Lorena Anghel, Görschwin Fey
A hybrid algorithm to conservatively check the robustness of circuits. 1-2 - Stephan Eggersglüß, Kohei Miyase, Xiaoqing Wen:
SAT-based post-processing for regional capture power reduction in at-speed scan test generation. 1-6 - Stavros Hadjitheophanous, Stelios N. Neophytou
Utilizing shared memory multi-cores to speed-up the ATPG process. 1-6 - Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski:
Transistor stuck-on fault detection tests for digital CMOS circuits. 1-6 - Erik Jan Marinissen
IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs. 1-10 - Erik Jan Marinissen
IoT: Source of test challenges. 1-10
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