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Vasily G. Moshnyaga
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- affiliation: Fukuoka University
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2020 – today
- 2024
- [c83]Yudai Inoue, Vasily G. Moshnyaga:
A Real-Time Detection of Patient's Aggressive Behaviors on a Smart Sensor. MWSCAS 2024: 911-914 - 2023
- [c82]Kaito Fukuda, Katsufumi Matsuguma, Yutaro Tabuchi, Ryutaro Ninomiya, Vasily G. Moshnyaga:
A Comparative Study of Sensing Technologies for Automatic Detection of Home Elopement. BioCAS 2023: 1-5 - [c81]Kaito Fukuda, Katsufumi Matsunaga, Yutaro Tabuchi, Ryutaro Ninomiya, Vasily G. Moshnyaga:
A Comparison of Sensing Technologies on a Room-Exit Detection System. SENSORS 2023: 1-4 - 2022
- [c80]Takayuki Imamura, Vasily G. Moshnyaga, Koji Hashimoto:
Automatic fall detection by using Doppler-radar and LSTM-based recurrent neural network. LifeTech 2022: 36-37 - [c79]Haruki Akaike, Shun-Ichi Katsuta, Shusaku Aramaki, Vasily G. Moshnyaga, Koji Hashimoto, Satoshi Ikeda:
Wandering Notification System for Caregivers of People with Dementia. MWSCAS 2022: 1-2 - [c78]Takayuki Imamura, Vasily G. Moshnyaga, Koji Hashimoto:
Fall detection with a single Doppler radar sensor and LSTM recurrent neural network. MWSCAS 2022: 1-4 - 2020
- [c77]Vasily G. Moshnyaga, Koji Hashimoto, Tomohiro Nogami, Kazuki Nojima:
A smart system for preventing people with dementia from falling from the chair. LifeTech 2020: 123-124
2010 – 2019
- 2019
- [c76]Vasily G. Moshnyaga, Koji Hashimoto, Tomohiro Nogami, Kazuki Nojima:
Design of wireless smart chair system for people with cognitive deficiency. MWSCAS 2019: 1219-1222 - [c75]Haruka Yoshino, Vasily G. Moshnyaga, Koji Hashimoto:
Fall Detection on a single Doppler Radar Sensor by using Convolutional Neural Networks. SMC 2019: 2889-2892 - 2018
- [c74]Sho Yamanaka, Vasily G. Moshnyaga:
New Method for Medical Intake Detection by Kinect. MWSCAS 2018: 218-221 - [c73]Vasily G. Moshnyaga, Juntaro Shioyama, Koji Hashimoto:
A Camera-Based Approach to Prevent Fingerprint Hacking. SiPS 2018: 235-240 - 2017
- [c72]Kasman, Vasily G. Moshnyaga:
A smart mat for assisting Muslims in praying. ICCE 2017: 462-465 - [c71]Akira Hayashida, Vasily G. Moshnyaga, Koji Hashimoto:
New approach for indoor fall detection by infrared thermal array sensor. MWSCAS 2017: 1410-1413 - [c70]Akira Hayashida, Vasily G. Moshnyaga, Koji Hashimoto:
The use of thermal ir array sensor for indoor fall detection. SMC 2017: 594-599 - 2016
- [c69]Vasily G. Moshnyaga:
Guidelines for developers of smart systems. IEEE Conf. on Intelligent Systems 2016: 455-460 - [c68]Vasily G. Moshnyaga, Masaki Koyanagi, Fumiyuki Hirayama, Akihisa Takahama, Koji Hashimoto:
A medication adherence monitoring system for people with dementia. SMC 2016: 194-199 - 2015
- [c67]Vasily G. Moshnyaga, Tanaka Osamu, Toshin Ryu, Koji Hashimoto:
Identification of Basic Behavioral Activities by Heterogeneous Sensors of In-Home Monitoring System. HBU 2015: 160-174 - [c66]Vasily G. Moshnyaga, Hideki Nita:
STG-based detection of power virus inputs in FSM. MWSCAS 2015: 1-4 - 2014
- [c65]Vasily G. Moshnyaga, Tanaka Osamu, Toshin Ryu, Akira Hayashida, Daiki Sakamoto, Yuki Imai, Takuma Shibata:
An intelligent system for assisting family caregivers of dementia people. CICARE 2014: 85-89 - [c64]Osamu Tanaka, Toshin Ryu, Akira Hayashida, Vasily G. Moshnyaga, Koji Hashimoto:
A Smart Carpet Design for Monitoring People with Dementia. ICSEng 2014: 653-659 - [c63]Tanaka Osamu, Toshin Ryu, Akira Hayashida, Vasily G. Moshnyaga, Daiki Sakamoto, Yuki Imai, Takuma Shibata:
A smart system for home monitoring of people with cognitive impairment. IHTC 2014: 1-4 - [c62]Akiya Baba, Nanoka Sumi, Vasily G. Moshnyaga:
Impact of computation offloading on efficiency of wireless face recognition. PATMOS 2014: 1-7 - [c61]Nanoka Sumi, Akiya Baba, Vasily G. Moshnyaga:
Effect of computation offload on performance and energy consumption of mobile face recognition. SiPS 2014: 19-25 - 2013
- [c60]Vasily G. Moshnyaga:
Want to green application software?: mind the target hardware. GIBSE@AOSD 2013: 1-2 - [c59]Vasily G. Moshnyaga:
Assessment of Software Lifecycle Energy and its Contribution to Green House Gas Emissions. CGC 2013: 197-198 - [c58]Keita Imaizumi, Vasily G. Moshnyaga:
Network-based face recognition on mobile devices. ICCE-Berlin 2013: 406-409 - [c57]Vasily G. Moshnyaga:
An assessment of software lifecycle energy. PATMOS 2013: 112-119 - [c56]Vasily G. Moshnyaga:
Lifecycle energy assessment of mobile applications. DeMobile@ESEC/FSE 2013: 17-23 - 2012
- [j11]Tomoaki Ando, Vasily G. Moshnyaga, Koji Hashimoto:
FPGA Design of User Monitoring System for Display Power Control. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2364-2372 (2012) - [j10]Vasily G. Moshnyaga, Koji Hashimoto, Tadashi Suetsugu:
A Camera-Driven Power Management of Computer Display. IEEE Trans. Circuits Syst. Video Technol. 22(11): 1542-1553 (2012) - [c55]Tomoaki Ando, Vasily G. Moshnyaga, Koji Hashimoto:
A low-power FPGA implementation of eye tracking. ICASSP 2012: 1573-1576 - [r1]Vasily G. Moshnyaga:
Understanding and Exploiting User Behavior for Energy Saving. Handbook of Energy-Aware and Green Computing 2012: 1145-1158 - 2011
- [c54]Choong Geun Lee, Vasily G. Moshnyaga, Koji Hashimoto:
Embedded System for Camera-Based TV Power Reduction. DSD 2011: 764-768 - [c53]Chungun Lee, Vasily G. Moshnyaga:
Embedded system for TV power reduction by viewer monitoring. ICME 2011: 1-4 - [c52]Choong Geun Lee, Vasily G. Moshnyaga:
TV energy management by camera-based viewer monitoring. ISCAS 2011: 949-952 - 2010
- [c51]Koji Hashimoto, Vasily G. Moshnyaga:
A Cost-Effective TCP/IP Offload Accelerator Design for Network Interface Controller. CDES 2010: 153-159 - [c50]Vasily G. Moshnyaga:
The use of eye tracking for PC energy management. ETRA 2010: 113-116 - [c49]Vasily G. Moshnyaga:
A new approach for energy management in user-centric applications. Green Computing Conference 2010: 107-112 - [c48]Takeaki Matsubara, Vasily G. Moshnyaga, Koji Hashimoto:
A FPGA implementation of low-complexity noise removal. ICECS 2010: 255-258
2000 – 2009
- 2009
- [c47]Vasily G. Moshnyaga, Koji Hashimoto, Shuhei Higashi:
A Hardware System for Tracking Eyes of Computer User. CDES 2009: 125-130 - [c46]Vasily G. Moshnyaga, Koji Hashimoto, Tadashi Suetsugu, Shuhei Higashi:
A Hardware Implementation of the User-Centric Display Energy Management. PATMOS 2009: 56-65 - [c45]Vasily G. Moshnyaga, Shinji Yamamoto:
Algorithm Optimizations for Low-Complexity Eye Tracking. SMC 2009: 18-22 - 2008
- [c44]Vasily G. Moshnyaga:
How to Really Save Computer Energy? CDES 2008: 89-95 - [c43]Vasily G. Moshnyaga, Koji Hashimoto, Tadashi Suetsugu:
A Hardware Design for Camera-Based Power Management of Computer Monitor. DSD 2008: 203-209 - [c42]Vasily G. Moshnyaga, Koji Hashimoto, Tadashi Suetsugu:
FPGA design for user's presence detection. ICECS 2008: 1316-1319 - [c41]Vasily G. Moshnyaga:
Untraditional Approach to Computer Energy Reduction. PATMOS 2008: 82-92 - [c40]Vasily G. Moshnyaga, Koji Hashimoto, Tadashi Suetsugu:
A hardware design of camera-based user's presence detector. SMC 2008: 429-432 - 2007
- [c39]Vasily G. Moshnyaga, Hua Vo, Glenn Reinman, Miodrag Potkonjak:
Reducing Energy of DRAM/Flash Memory System by OS-controlled Data Refresh. ISCAS 2007: 2108-2111 - 2006
- [c38]Koji Hashimoto, Vasily G. Moshnyaga, Kazuaki J. Murakami:
Circuit Area-latency Optimization Technique for High-precision Elementary Functions. APCCAS 2006: 1406-1409 - [c37]Vasily G. Moshnyaga, Kenji Wakisaka:
Reducing computations in MPEG2 video decoder. ISCAS 2006 - [c36]Vasily G. Moshnyaga, S. Yamaoka:
MPEG complexity reduction by scene adaptive motion estimation. ISCAS 2006 - [c35]Vasily G. Moshnyaga, Hoa Vo, Glenn Reinman, Miodrag Potkonjak:
Handheld System Energy Reduction by OS-Driven Refresh. PATMOS 2006: 24-35 - 2005
- [j9]Reiko Komiya, Koji Inoue, Vasily G. Moshnyaga, Kazuaki J. Murakami:
Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 862-868 (2005) - [j8]Vasily G. Moshnyaga, Tomoyuki Yamanaka:
Multiplier Energy Reduction by Dynamic Voltage Variation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3548-3553 (2005) - [c34]Vasily G. Moshnyaga, Naoki Migita, Kenji Wakisaka:
Reduction of MPEG2 video decoding computations. Circuits, Signals, and Systems 2005: 218-221 - [c33]Vasily G. Moshnyaga, Eiji Morikawa:
LCD Display Energy Reduction by User Monitoring. ICCD 2005: 94-97 - [c32]Vasily G. Moshnyaga, Eiji Morikawa:
Reducing Energy Consumption of Computer Display by Camera-Based User Monitoring. PATMOS 2005: 528-539 - 2004
- [c31]Kentaro Hamayasu, Vasily G. Moshnyaga:
Impact of Register-Cache Bandwidth Variation on Processor Performance. Asia-Pacific Computer Systems Architecture Conference 2004: 212-225 - [c30]Tomoyuki Yamanaka, Vasily G. Moshnyaga:
Reducing multiplier energy by data-driven voltage variation. ISCAS (2) 2004: 285-288 - [c29]Vasily G. Moshnyaga, Koichi Masunaga, Naoki Kajiwara:
A data reusing architecture for MPEG video coding. ISCAS (3) 2004: 797-800 - [c28]Koji Inoue, Hidekazu Tanaka, Vasily G. Moshnyaga, Kazuaki J. Murakami:
A low-power I-cache design with tag-comparison reuse. SoC 2004: 61-67 - 2003
- [j7]Koji Inoue, Vasily G. Moshnyaga, Kazuaki J. Murakami:
Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(4): 799-805 (2003) - [j6]Vasily G. Moshnyaga:
Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits. J. VLSI Signal Process. 33(1-2): 75-82 (2003) - [c27]Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga:
Reducing Access Count to Register-Files through Operand Reuse. Asia-Pacific Computer Systems Architecture Conference 2003: 112-121 - [c26]Masayoshi Fujino, Vasily G. Moshnyaga:
Dynamic operand transformation for low-power multiplier-accumulator design. ISCAS (5) 2003: 345-348 - 2002
- [j5]Vasily G. Moshnyaga:
Adaptive Bitwidth Compression for Low Power Video Memory Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(4): 797-803 (2002) - [j4]Vasily G. Moshnyaga:
Reducing energy dissipation of frame memory by adaptive bit-width compression. IEEE Trans. Circuits Syst. Video Technol. 12(8): 713-718 (2002) - [c25]Koji Inoue, Vasily G. Moshnyaga, Kazuaki J. Murakami:
Reducing power consumption of instruction ROMs by exploiting instruction frequency. APCCAS (2) 2002: 1-6 - [c24]Jun-ni Ohban, Vasily G. Moshnyaga, Koji Inoue:
Multiplier energy reduction through bypassing of partial products. APCCAS (2) 2002: 13-17 - [c23]Vasily G. Moshnyaga:
Reduction of memory accesses in motion estimation by block-data reuse. ICASSP 2002: 3128-3131 - [c22]Koji Inoue, Vasily G. Moshnyaga, Kazuaki J. Murakami:
A Low Energy Set-Associative I-Cache with Extended BTB. ICCD 2002: 187- - [c21]Mitsumasa Fujino, Vasily G. Moshnyaga:
An efficient Hamming distance comparator for low-power applications. ICECS 2002: 641-644 - [c20]Vasily G. Moshnyaga:
Reducing energy dissipation of video memory by adaptive bit-width compression. ICECS 2002: 831-834 - [c19]Vasily G. Moshnyaga, Koji Inoue, Mizuka Fukagawa:
Reducing energy consumption of video memory by bit-width compression. ISLPED 2002: 142-147 - [c18]Koji Inoue, Vasily G. Moshnyaga, Kazuaki J. Murakami:
A history-based I-cache for low-energy multimedia applications. ISLPED 2002: 148-153 - [c17]Koji Inoue, Vasily G. Moshnyaga, Kazuaki J. Murakami:
Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints. PACS 2002: 18-32 - [c16]Hiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga:
Register File Energy Reduction by Operand Data Reuse. PATMOS 2002: 278-288 - 2001
- [j3]Vasily G. Moshnyaga:
A new computationally adaptive formulation of block-matching motion estimation. IEEE Trans. Circuits Syst. Video Technol. 11(1): 118-124 (2001) - [c15]Vasily G. Moshnyaga:
Reducing cache engery through dual voltage supply. ASP-DAC 2001: 302-305 - [c14]Vasily G. Moshnyaga, Hiroshi Tsuji:
Cache energy reduction by dual voltage supply. ISCAS (4) 2001: 922-925 - [c13]Vasily G. Moshnyaga:
Energy reduction in queues and stacks by adaptive bitwidth compression. ISLPED 2001: 22-27 - 2000
- [c12]Vasily G. Moshnyaga, Kazuhito Nakasima:
An architectural enhancement for reducing background computation in adaptive motion estimation. ICASSP 2000: 3374-3377 - [c11]Vasily G. Moshnyaga, Kazuhito Nakasima:
Reduction of background computations in adaptive block-matching motion estimation. ISCAS 2000: 667-670
1990 – 1999
- 1999
- [c10]Vasily G. Moshnyaga:
An adaptive block-matching algorithm for motion estimation. ICASSP 1999: 1953-1956 - [c9]Vasily G. Moshnyaga:
A new architecture for computationally adaptive full-search block-matching motion estimation. ISCAS (4) 1999: 219-222 - [c8]Vasily G. Moshnyaga:
An MSB truncation scheme for low-power video processors. ISCAS (4) 1999: 291-294 - 1998
- [j2]Vasily G. Moshnyaga, Naoto Watanabe, Keikichi Tamaru:
A memory efficient array architecture for real-time motion estimation. Syst. Comput. Jpn. 29(9): 13-20 (1998) - [c7]Vasily G. Moshnyaga, Kazuhiro Suzuki, Keikichi Tamaru:
A new architecture for in-memory image convolution. ICASSP 1998: 3001-3004 - 1997
- [c6]Vasily G. Moshnyaga, Keikichi Tamaru:
A memory efficient array architecture for full-search block matching algorithm. ICASSP 1997: 4109-4112 - [c5]Vasily G. Moshnyaga, Keikichi Tamaru:
A Memory Efficient Array Architecture for Real-Time Motion Estimation. IPPS 1997: 28-32 - 1995
- [j1]Vasily G. Moshnyaga, Yutaka Mori, Keikichi Tamaru:
Register-Transfer Module Selection for Sub-Micron ASIC Design. IEICE Trans. Inf. Syst. 78-D(3): 252-255 (1995) - [c4]Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi Tamaru:
A scheduling algorithm for synthesis of bus-partitioned architectures. ASP-DAC 1995 - [c3]Vasily G. Moshnyaga, Keikichi Tamaru:
A Comparative Study of Switching Activity Reduction Techniques for Design of Low-Power Multipliers. ISCAS 1995: 1560-1563 - 1993
- [c2]Vasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru:
Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's. ICCAD 1993: 100-103 - 1992
- [c1]Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura:
Design of data-path module generators from algorithmic representations. Synthesis for Control Dominated Circuits 1992: 183-192
Coauthor Index
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last updated on 2024-10-11 18:22 CEST by the dblp team
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