In this paper we propose an algorithm that combines module selection with Performance-Driven module placement and reduces an impact of wiring on sub-micron ASIC ...

This paper proposes a new algorithm that incorporates performance-driven placement in module selection phase of the synthesis. The algorithm not only ...

This paper proposes a new algo- rithm that incorporates Performance-Driven Placement in module selection phase of the synthesis. The algorithm not only ...

The ASIC Design Methodology Primer provides an overview of the steps involved in application specific integrated circuit (ASIC) design.

This paper presents a tool for generating a performance-driven placement from a netlist of Register-Transfer Level (RTL) blocks.

This paper deals with study and implementation of practices to get better PPA in ASIC physical design which is applicable to all digital circuits, both ...

Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's pp. 100,101,102,103. Design tool integration using object-oriented database ...

Dec 30, 1997 · Based on the overall system architecture, a Register Transfer Level (RTL) model is developed with a Hardware Description Language (HDL), such as ...

Nov 7, 1993 · Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's. + 4. Pages 100–103. 1; 129. Metrics. Total Citations1.

An RTL fault-list is created for each RTL module using the proposed fault model and fault-injection algorithm. RTL modules are then synthesized using the ...