default search action
SoCC 2004: Santa Clara, CA, USA
- Proceedings 2004 IEEE International SOC Conference, September 12-15, 2004, Hilton Santa Clara, CA, USA. IEEE 2004, ISBN 0-7803-8445-8
- Sung-Mo Kang:
Message from the General Chair. 0 - Dong S. Ha:
Message from the Technical Program Chair. 0 - Amir Hosein Kamalizad, Richard Plettner, Chengzhi Pan, Nader Bagherzadeh:
Fast parallel soft Viterbi decoder mapping on a reconfigurable DSP platform. 3-6 - Imran Ahmed, Tughrul Arslan, Sami Khawam:
Video transmission through domain specific reconfigurable architecurtes over short distance wireless medium utilizing Bluetooth IEEE 802.15.1™ standard [architecurtes read architectures]. 7-10 - Salvador Mir, Benoît Charlot, Libor Rufer
, Bernard Courtois:
On-chip testing of embedded silicon transducers. 13-18 - Wenxin Wang, Mohab Anis, Shawki Areibi:
Fast techniques for standby leakage reduction in MTCMOS circuits. 21-24 - Hassan Hassan, Mohab Anis, Mohamed I. Elmasry:
Analysis and design of low-power multi-threshold MCML. 25-29 - Sunny Nahata, Kyusun Choi, Jincheol Yoo:
A high-speed power and resolution adaptive flash analog-to-digital converter. 33-36 - Andreas Larsson, Sameer R. Sonkusale:
A background calibration scheme for pipelined ADCs including non-linear operational amplifier gain and reference error correction. 37-40 - Ayman H. Ismail
Analog-to-digital conversion for SONET OC-192. 41-44 - Saiyu Ren, Ray Siferd, Robert Blumgold:
Parallel time interleaved delta sigma band pass analog to digital converter for SOC applications. 45-48 - Makoto Saen, Motohiro Nakagawa, Junichi Nishimoto, Tomoyuki Kodama, Fumio Arakawa:
Transparent SOC: on-chip analyzing techniques and implementation for embedded processor. 51-54 - Jian Liu, Li-Rong Zheng, Hannu Tenhunen:
A circuit-switched network architecture for network-on-chip. 55-58 - Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili:
Clock tree tuning using shortest paths polygon. 59-62 - Tsung-Yi Ho
Multilevel routing with jumper insertion for antenna avoidance. 63-66 - Radu M. Secareanu, Qiang Li, Sushil Bharatan, Carl Kyono, Rainer Thoma, Mel Miller, Olin L. Hartin:
Signal integrity implications of inductor-to-circuit proximity. 69-72 - Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry:
POMR: a power-optimal maze routing methodology. 73-77 - Kaveh Shakeri, Muhannad S. Bakir, James D. Meindl:
Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution. 78-81 - Praveen Elakkumanan, Vishwanath Ananthakrishnan, Ashok Narasimhan, Ramalingam Sridhar:
Leakage aware SER reduction technique for UDSM logic circuits. 82-85 - Tejasvi Das, Ghanshyam Nayak, Ponnathpur R. Mukund:
A generic macromodel for coupling between inductors and interconnects for R.F.I.C. layouts. 89-92 - Xiaohua Fan, Edgar Sánchez-Sinencio:
3-22GHz CMOS distributed single-balanced mixer. 93-96 - Hassan Hassan, Mohab Anis, Mohamed I. Elmasry:
Impact of technology scaling on RF CMOS. 97-101 - Patrick Birrer, Terri S. Fiez, Kartikeya Mayaram:
Silencer!: a tool for substrate noise coupling analysis. 105-108 - Donghoon Han, Abhijit Chatterjee:
Adaptive response surface modeling-based method for analog circuit sizing. 109-112 - Bo Wan, Pavel V. Nikitin, Chuanjin Richard Shi:
Circuit level modeling and simulation of mixed-technology systems. 113-116 - Byung-Tae Kang, Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides:
Power-efficient implementation of turbo decoder in SDR system. 119-122 - Hanho Lee:
A power-aware scalable pipelined Booth multiplier. 123-126 - C. H. Wang, Ahmet T. Erdogan
High throughput and low power FIR filtering IP cores. 127-130 - Brian A. Jackson, James R. Armstrong:
Synthesis of SystemC models from SDF Ptolemy descriptions. 133-134 - Håkan Bengtson, Christer Svensson:
A scalable and robust rail-to-rail delay cell for DLLs. 135-136 - Charoensak Charayaphan, Saman S. Abeysekera:
FPGA implementation of efficient Kalman band-pass sigma-delta filter for application in FM demodulation. 137-138 - Charoensak Charayaphan, Farook Sattar
System-level design of low-cost FPGA hardware for real-time ICA-based blind source separation. 139-140 - Filippo Mondinelli, Michele Borgatti, Zsolt Miklós Kovács-Vajna:
A 0.13μm 1Gb/s/channel store-and-forward network on-chip. 141-142 - Nam-Hoon Kim, Peter A. Beerel, Ralph Peng:
A memory allocation and assignment method using multiway partitioning. 143-144 - Yu-Hsiung Huang, Mely Chen Chi:
Low-power driven standard-cell placement based on a multilevel force-directed algorithm. 145-146 - Henrik Fredriksson, Christer Svensson:
Mixed-signal DFE for multi-drop, gb/s, memory buses - a feasibility study. 147-148 - Ralph Oberhuber, Christoph Hechtl, Klaus Schimpf, Berthold Staufer:
Bandgap yield loss due to dislocations on RFSiGe transceiver ICs: failure analysis, design. 149-150 - Kahn Li Lim, Zeljko Zilic:
A novel phase detector for PAM-4 clock recovery in high speed serial links. 151-152 - Yao Gang, Tughrul Arslan, Ahmet T. Erdogan
An efficient reformulation based architecture for adaptive forward error correction decoding in wireless applications. 153-154 - Kyoung-Hoi Koo, Jin-Ho Seo, Myeong-Lyong Ko, Jae-Whui Kim:
A new level shifter in ultra deep sub-micron for low to wide range voltage applications. 155-156 - Jeemyong Lee, Wooseok Kwon, Sanghun Lee, Chanho Lee:
Design of a programmable cryptoprocessor for multiple cryptosystems. 157-158 - Ciaran Toal, Sakir Sezer:
Exploration of GFP frame delineation architectures for network processing. 159-162 - Arindam Mukherjee:
Reducing crosstalk noise in high speed FPGAs. 163-164 - Jürgen Becker, Martin Vorbach:
Coarse-grain reconfigurable XPP devices for adaptive high-end mobile video-processing. 165-166 - Kalle Folkesson, Christer Svensson:
Robust multi-phase clock generation with reduced jitter. 167-168 - Martin Hansson, Atila Alvandpour:
A low clock load conditional flip-flop. 169-170 - Zemo Yang, Samiha Mourad:
Crosstalk induced fault analysis in DRAMs. 171-172 - Visvesh S. Sathe, Conrad H. Ziesler, Marios C. Papaefthymiou, Suhwan Kim, Stephen V. Kosonocky:
A synchronous interface for SoCs with multiple clock domains. 173-174 - Nikolas Stefanou
Achieving higher dynamic range in flash A/D converters. 175-176 - Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo:
Low energy transmission coding for on-chip serial communications. 177-178 - Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman:
Clock tree layout design for reduced delay uncertainty. 179-180 - Gerard Boudon, Alan Wall, Joe Foster, Barry Wolford, John Fakiris:
A 800 MHz PowerPC SOC with PCI-X DDR266, DDRII-667, and RAID assist. 183-186 - Steven Eustis:
An embedded read only memory architecture with a complementary and two interchangeable power/performance design points. 187-190 - Theocharis Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin, Vamsi Srikantam:
A generic reconfigurable neural network architecture as a network on chip. 191-194 - Raid Ayoub, Peter Petrov, Alex Orailoglu:
Application specific instruction memory transformations for power efficient, fault resilient embedded processors. 195-198 - Pascal Nsame, Yvon Savaria:
Multi-processor SoC integration: a case study on BlueGene/L. 201-204 - Tiberiu Seceleanu:
Communication on a segmented bus. 205-208 - Maxim Konakov, Jae-Wook Lee, Junghyun Lee, Eun-Jin Ryu, Eingseob Cho, Jungeun Lee, Hyunsu Chae, Jeongwon Lee:
High speed mixed analog/digital PRML architecture for optical data storage system. 209-212 - Yun Long, Chunhui Zhang, Fadi J. Kurdahi:
A high-performance parallel mode EBCOT encoder architecture design for JPEG2000. 213-216 - Jihyun Lee, Young-Jun Lee, Yong-Bin Kim:
SRAM word-oriented redundancy methodology using built in self-repair. 219-222 - Jong-Sun Kim, Min-Su Hwang, Seungsu Roh, Ja-Young Lee, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo:
On-chip network based embedded core testing. 223-226 - Srivathsan Krishnamohan, Nihar R. Mahapatra:
An efficient error-masking technique for improving the soft-error robustness of static CMOS circuits. 227-230 - Maged Ghoneima, Yehea I. Ismail:
Low-power on-chip bus architecture using dynamic relative delays. 233-236 - Balasubramanian Sethuraman, Jawad Khan, Ranga Vemuri:
Battery-efficient task execution on portable reconfigurable computing. 237-240 - Amit Agarwal, Kaushik Roy, Ram K. Krishnamurthy:
A leakage-tolerant low-leakage register file with conditional sleep transistor. 241-244 - Hassan Hassan, Mohab Anis, Mohamed I. Elmasry:
MOS current mode logic: design, optimization, and variability. 247-250 - Michael Wieckowski, Martin Margala:
A 32Kb SRAM cache using current mode operation and asynchronous wave-pipelined decoders. 251-254 - Ming-Ta Hsieh, Gerald E. Sobelman:
Simultaneous bidirectional PAM-4 link with built-in self-test. 255-258 - Arindam Mukherjee, Rajsaktish Sankaranarayan:
Retiming and clock scheduling to minimize simultaneous switching. 259-262 - Xiaoning Nie, Ulf Nordqvist, Lajos Gazsi, Dake Liu:
Network processors for access network (NP4AN): trends and challenges. 265-269 - Colm McKillen, Sakir Sezer:
A weighted fair queuing finishing tag computation architecture and implementation. 270-273 - Tomaz Feliciian, Stephen B. Furber:
An asynchronous on-chip network router with quality-of-service (QoS) support. 274-277 - Minoru Watanabe, Fuminori Kobayashi:
An optically differential reconfigurable gate array using a 0.18 μm CMOS process. 281-284 - Jingzhao Ou, Viktor K. Prasanna:
Rapid energy estimation of computations on FPGA based soft processors. 285-288 - Nikolay Kavaldjiev, Gerard J. M. Smit, Pierre G. Jansen:
A virtual channel router for on-chip networks. 289-293 - Marcus van Ierssel, Joyce Wong, Ali Sheikholeslami:
An adaptive 4-PAM decision-feedback equalizer for chip-to-chip signaling. 297-300 - Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske:
Substrate noise optimization in early floorplanning for mixed signal SOCs. 301-304 - Sanghun Lee, Chanho Lee, Hyuk-Jae Lee:
A new multi-channel on-chip-bus architecture for system-on-chips. 305-308 - Vishal Gupta, Gabriel A. Rincón-Mora, Prasun Raha:
Analysis and design of monolithic, high PSR, linear regulators for SoC applications. 311-315 - Franz Schlögl, Horst Dietrich, Horst Zimmermann:
High-gain high-speed operational amplifier in digital 120nm CMOS. 316-319 - Sripriya R. Bandi, Ponnathpur R. Mukund:
A compensation technique for transistor mismatch in current mirrors. 320-323 - Jee-Youl Ryu, Bruce C. Kim:
A new design for built-in self-test of 5GHz low noise amplifiers. 324-327 - Mikhail Popovich, Eby G. Friedman:
Decoupling capacitors for power distribution systems with multiple power supply voltages. 331-334 - Guoqing Chen, Eby G. Friedman:
Low power repeaters driving RC interconnects with delay and bandwidth constraints. 335-339 - Yuantao Peng, Xun Liu:
Global interconnect optimization with simultaneous macrocell placement and repeater insertion. 340-343 - Junmou Zhang, Eby G. Friedman:
Mutual inductance modeling for multiple RLC interconnects with application to shield insertion. 344-347 - Qiurong He, Milton Feng:
A novel half-rate architecture for high-speed clock and data recovery. 351-354 - Wonjae Lee, Sangyun Hwang, Minho Kwon, Seongjoo Lee, Jaeseok Kim:
SoC design of remote terminals for wireless telemetry system. 355-358 - Xiaomin Chen, Sayfe Kiaei:
An improved delay-hopped transmitted-reference ultra wideband architecture. 359-362 - Chao Wang, Yit-Chow Tong, Yu Shao:
VLSI design and analysis of a critical-band processor for speech recognition. 365-368 - Xiaofeng Wu, Vassilios A. Chouliaras, Roger Goodall:
An application-specific processor hard macro for real-time control. 369-372 - Ireneusz Janiszewski, Hermann Meuth, Bernhard Hoppe:
FPGA-efficient phase-to-I/Q architecture. 373-376 - Jiandong Ge, Anh Dinh:
A 3.8Ghz channel-select filter using 0.18μm CMOS. 379-382 - Nazanin Darbanian, Sayfe Kiaei, Shahin Farahani:
Optimum design and trade-offs for a triple-band LNA for GSM, WCDMA and GPS applications. 383-386 - Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner:
Extended dynamic voltage scaling for low power design. 389-394 - Yuh-Fang Tsai, Ananth Hegde Ankadi, Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides:
ChipPower: an architecture-level leakage simulator. 395-398 - Mrinmoy Ghosh, Weidong Shi, Hsien-Hsin S. Lee:
CoolPression - a hybrid significance compression technique for reducing energy in caches. 399-402
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-15 19:46 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: