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Bob Schell
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2020 – today
- 2020
- [c4]Hajime Shibata, Gerry Taylor, Bob Schell, Victor Kozlov, Sharvil Patil, Donald Paterson, Asha Ganesan, Yunzhi Dong, Wenhua Yang, Yue Yin, Zhao Li, Prawal Shrestha, Athreya Gopal, Aathreya S. Bhat
, Shanthi Pavan:
16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter. ISSCC 2020: 260-262
2010 – 2019
- 2018
- [c3]Bob Schell, Robert Bishop, Jack Kenney:
A 3-12.5 Gb/s Reference-Less CDR for an Eye-Opening Monitor. ESSCIRC 2018: 186-189
2000 – 2009
- 2009
- [j3]Bob Schell, Yannis P. Tsividis:
Analysis and simulation of continuous-time digital signal processors. Signal Process. 89(10): 2013-2026 (2009) - 2008
- [j2]Bob Schell, Yannis P. Tsividis:
A Low Power Tunable Delay Element Suitable for Asynchronous Delays of Burst Information. IEEE J. Solid State Circuits 43(5): 1227-1234 (2008) - [j1]Bob Schell, Yannis P. Tsividis:
A Continuous-Time ADC/DSP/DAC System With No Clock and With Activity-Dependent Power Dissipation. IEEE J. Solid State Circuits 43(11): 2472-2481 (2008) - [c2]Bob Schell, Yannis P. Tsividis:
A Clockless ADC/DSP/DAC System with Activity-Dependent Power Dissipation and No Aliasing. ISSCC 2008: 550-551 - 2007
- [c1]Bob Schell, Yannis P. Tsividis:
Analysis of Continuous-Time Digital Signal Processors. ISCAS 2007: 2232-2235
Coauthor Index
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