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2020 – today
- 2024
- [c71]Haoyu Gong, Wen-Liang Zeng, Mingqiang Guo, Chi-Seng Lam, Shulin Zhao, Rui Paulo Martins, Sai-Weng Sin:
A 75dB-SNDR 10MHz-BW 2-Channel Time-Interleaved Noise-Shaping SAR ADC Directly Powered by an On-Chip DC-DC Converter. CICC 2024: 1-2 - [c70]Ke Li, Xianyu Congzhou, Liang Qi, Mingqiang Guo, Rui Paulo Martins, Sai-Weng Sin:
A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering. CICC 2024: 1-2 - [c69]Xinyu Qin, Yichen Jin, Guoxing Wang, Sai-Weng Sin, Maurits Ortmanns, Yong Lian, Liang Qi:
A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2-2 CT DSM in 65nm CMOS. CICC 2024: 1-2 - [c68]Ran Zhang, Ka-Fai Un, Mingqiang Guo, Liang Qi, Dengke Xu, Weibing Zhao, Rui Paulo Martins, Franco Maloberti, Sai-Weng Sin:
A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation. ISCAS 2024: 1-5 - 2023
- [j59]Ya-Jie Wu
, Ricardo Brito, Wai-Hei Choi
IoT Cloud-Edge Reconfigurable Mixed-Signal Smart Meter Platform for Arc Fault Detection. IEEE Internet Things J. 10(2): 1682-1695 (2023) - [j58]Shulin Zhao
A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time- Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward. IEEE J. Solid State Circuits 58(10): 2722-2732 (2023) - [j57]Caolei Pan
A 95% Peak Efficiency Modified KY Converter With Improved Flying Capacitor Charging in DCM for IoT Applications. IEEE J. Solid State Circuits 58(11): 3219-3230 (2023) - [j56]Yue Hu, Yuekai Liu
A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4729-4741 (2023) - [j55]Mingqiang Guo
A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4767-4780 (2023) - [j54]Gaofeng Tan, Xinyu Qin, Yan Liu
A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4781-4792 (2023) - [j53]Jingying Zhang
On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 356-360 (2023) - [j52]Kaiquan Chen
A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order. IEEE Trans. Circuits Syst. II Express Briefs 70(8): 2724-2728 (2023) - [c67]Ruiqi Gao, Mingqiang Guo
Weightings in Incremental ADCs: A Tutorial Review. CICC 2023: 1-8 - [c66]Wen-Liang Zeng, Guigang Cai, Chon-Fai Lee, Chi-Seng Lam, Yan Lu, Sai-Weng Sin, Rui Paulo Martins:
A 12V-lnput 1V-1.8V-Output 93.7% Peak Efficiency Dual-Inductor Quad-Path Hybrid DC-DC Converter. ISSCC 2023: 200-201 - 2022
- [j51]Danfeng Zhai
High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4944-4957 (2022) - [j50]Mingqiang Guo
Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2564-2569 (2022) - [j49]Liang Qi
Wideband Continuous-Time MASH Delta-Sigma Modulators: A Tutorial Review. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2623-2628 (2022) - [j48]Ya-Jie Wu
An FPGA-Based Self-Reconfigurable Arc Fault Detection System for Smart Meters. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 4133-4137 (2022) - [c65]Mingqiang Guo, Sai-Weng Sin, Liang Qi, Gang Xiao, Rui Paulo Martins:
A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing. CICC 2022: 1-2 - [c64]Ke Li, Sai-Weng Sin, Liang Qi, Weibing Zhao, Guoxing Wang, Rui Paulo Martins:
A Robust Hybrid CT/DT 0-2 MASH DSM with Passive Noise-Shaping SAR ADC. ISCAS 2022: 551-555 - 2021
- [j47]Rui Paulo Martins
Bird's-eye view of analog and mixed-signal chips for the 21st century. Int. J. Circuit Theory Appl. 49(3): 746-761 (2021) - [j46]Dongyang Jiang
A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation. IEEE J. Solid State Circuits 56(8): 2375-2387 (2021) - [c63]Liang Qi, Xinyu Qin, Sai-Weng Sin, Chixiao Chen, Fan Ye, Guoyong Shi, Guoxing Wang:
Advances in Continuous-time MASH ΔΣ Modulators. ASICON 2021: 1-4 - [c62]Wen-Liang Zeng, Caolei Pan, Chi-Seng Lam, Sai-Weng Sin, Chenchang Zhan, Rui Paulo Martins:
A 95% Peak Efficiency Modified KY (Boost) Converter for IoT with Continuous Flying Capacitor Charging in DCM. A-SSCC 2021: 1-3 - [c61]Xinyu Qin, Jingying Zhang, Liang Qi, Sai-Weng Sin, Rui Paulo Martins, Guoxing Wang:
Discrete-Time MASH Delta-Sigma Modulator with Second-Order Digital Noise Coupling for Wideband High-Resolution Applications. ISCAS 2021: 1-5 - [c60]Mingqiang Guo
Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs. ISOCC 2021: 248-249 - 2020
- [j45]Mingqiang Guo
A 5 GS/s 29 mW Interleaved SAR ADC With 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications. IEEE Access 8: 138944-138954 (2020) - [j44]Wen-Ming Zheng, Wen-Liang Zeng, Chi-Wa U
Analysis, Design and Control of an Integrated Three-Level Buck Converter under DCM Operation. J. Circuits Syst. Comput. 29(1): 2050011:1-2050011:20 (2020) - [j43]Liang Qi
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance. IEEE J. Solid State Circuits 55(2): 344-355 (2020) - [j42]Mingqiang Guo
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration. IEEE J. Solid State Circuits 55(3): 693-705 (2020) - [j41]Wen-Liang Zeng
A SAR-ADC-Assisted DC-DC Buck Converter With Fast Transient Recovery. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1669-1673 (2020) - [j40]Ji-Xuan Li
Digital Battery Management Unit With Built-In Resistance Compensation, Modulated Frequency Detection and Multi-Mode Protection for Fast, Efficient and Safe Charging. IEEE Trans. Circuits Syst. 67-I(11): 4063-4074 (2020) - [j39]Wen-Liang Zeng
A 470-nA Quiescent Current and 92.7%/94.7% Efficiency DCT/PWM Control Buck Converter With Seamless Mode Selection for IoT Application. IEEE Trans. Circuits Syst. 67-I(11): 4085-4098 (2020) - [j38]Hanyu Wang
LDO-Free Power Management System: A 10-bit Pipelined ADC Directly Powered by Inductor-Based Boost Converter With Ripple Calibration. IEEE Trans. Circuits Syst. 67-I(12): 4174-4186 (2020) - [c59]Dongyang Jiang
A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j37]Biao Wang
A 550- $\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS. IEEE J. Solid State Circuits 54(4): 1161-1172 (2019) - [j36]U-Fat Chio
An Integrated DC-DC Converter With Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery. IEEE J. Solid State Circuits 54(10): 2637-2648 (2019) - [j35]Wen-Liang Zeng
Design of KY Converter With Constant On-Time Control Under DCM Operation. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1753-1757 (2019) - [j34]Jianwei Liu
Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 481-485 (2019) - [c58]Liang Qi, Sai-Weng Sin
Multibit Sturdy MASH ΔΣ Modulator with Error-shaped Segmented DACs for Wideband Low-power Applications. ASICON 2019: 1-4 - [c57]Biao Wang, Sai-Weng Sin
A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS. A-SSCC 2019: 117-120 - [c56]Junhao Liang, Sai-Weng Sin
A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator. A-SSCC 2019: 309-312 - [c55]Mingqiang Guo
A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration. CICC 2019: 1-4 - [c54]Liang Qi, Ankesh Jain
A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS. ISSCC 2019: 336-338 - [c53]Mingqiang Guo
A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing. VLSI Circuits 2019: 76- - 2018
- [j33]Yu-Jun Mao, Chi-Seng Lam
Review and Selection Strategy for High-Accuracy Modeling of PWM Converters in DCM. J. Electr. Comput. Eng. 2018: 3901693:1-3901693:16 (2018) - [j32]Wei Wei Qin, Sai-Weng Sin
Quick and cost-efficient A/D converter static characterization using low-precision testing signal. Microelectron. J. 74: 86-93 (2018) - [j31]Jiaji Mao, Mingqiang Guo
A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1380-1384 (2018) - [j30]Da Feng
A 10-MHz Bandwidth Two-Path Third-Order ΣΔ Modulator With Cross-Coupling Branches. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1410-1414 (2018) - [j29]Ya-Jie Wu
A Reconfigurable and Extendable Digital Architecture for Mixed Signal Power Electronics Controller. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1480-1484 (2018) - [j28]Wen-Liang Zeng
A 220-MHz Bondwire-Based Fully-Integrated KY Converter With Fast Transient Response Under DCM Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3984-3995 (2018) - [c52]U. Fat Chio, Kuo-Chih Wen, Sai-Weng Sin
An Integrated DC-DC Converter with Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery. A-SSCC 2018: 31-32 - [c51]Jianyang Deng, Chi-Seng Lam
A Power Quality Indexes Measurement System Platform with Remote Alarm Notification. IECON 2018: 3461-3465 - [c50]Yiwei Tan, Chi-Seng Lam
Design and Control of An Integrated 3-Level Boost Converter under DCM Operation. ISCAS 2018: 1-5 - [c49]Biao Wang, Sai-Weng Sin
A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS. VLSI Circuits 2018: 207-208 - 2017
- [j27]Ziyang Luo, Yan Lu, Mo Huang
A sub-1V 78-nA bandgap reference with curvature compensation. Microelectron. J. 63: 35-40 (2017) - [j26]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin
Metastablility in SAR ADCs. IEEE Trans. Circuits Syst. II Express Briefs 64-II(2): 111-115 (2017) - [j25]Yan Lu, Haojuan Dai, Mo Huang
A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs 64-II(2): 166-170 (2017) - [j24]Jianyu Zhong
A 12b 180MS/s 0.068mm2 With Full-Calibration-Integrated Pipelined-SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(7): 1684-1695 (2017) - [j23]Chi-Hang Chan
A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(8): 1966-1976 (2017) - [j22]Liang Qi
A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(10): 2641-2654 (2017) - [j21]Arshad Hussain
Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 364-374 (2017) - [j20]Dezhi Xing
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1168-1172 (2017) - [c48]U. Fat Chio, Sai-Weng Sin
A 5-bit 2 GS/s binary-search ADC with charge-steering comparators. A-SSCC 2017: 221-224 - [c47]Chi-Wa U
CCM operation analysis and parameters design of Negative Output Elementary Luo Converter for ripple suppression. IECON 2017: 4867-4871 - [c46]Xia Du
A digital PWM controlled KY step-up converter based on frequency domain ΣΔ ADC. ISIE 2017: 561-564 - 2016
- [j19]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC. IEEE J. Solid State Circuits 51(2): 365-377 (2016) - [j18]Mo Huang
A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation. IEEE Trans. Circuits Syst. II Express Briefs 63-II(7): 683-687 (2016) - [j17]Mo Huang
Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators. IEEE Trans. Circuits Syst. II Express Briefs 63-II(9): 903-907 (2016) - [j16]Jianwei Liu, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2603-2607 (2016) - [c45]Yuan Ren, Sai-Weng Sin
A high DR multi-channel stage-shared hybrid front-end for integrated power electronics controller. A-SSCC 2016: 57-60 - [c44]Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin
A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction. ESSCIRC 2016: 169-172 - [c43]Dante Gabriel Muratore
An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology. ESSCIRC 2016: 421-424 - [c42]Wei Li, Sai-Weng Sin
A 94-dB DR, 105-Hz bandwidth interface circuit for inertial navigation applications. ISIC 2016: 1-4 - 2015
- [j15]Da Feng, Franco Maloberti, Sai-Weng Sin
Polyphase Decomposition for Tunable Band-Pass Sigma-Delta A/D Converters. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(4): 537-547 (2015) - [j14]Jianyu Zhong, Yan Zhu, Sai-Weng Sin
Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(9): 2196-2206 (2015) - [c41]Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin
A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation. A-SSCC 2015: 1-4 - [c40]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin
26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS. ISSCC 2015: 1-3 - [c39]Yan Lu
20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors. ISSCC 2015: 1-3 - 2014
- [j13]Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin
Split-SAR ADCs: Improved Linearity With Power and Speed Optimization. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 372-383 (2014) - [c38]Da Feng, Franco Maloberti, Sai-Weng Sin
Jitter-resistant Capacitor Based Sine-Shaped DAC for Continuous-Time Sigma-Delta modulators. ISCAS 2014: 1348-1351 - 2013
- [j12]Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin
A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. IEEE J. Solid State Circuits 48(8): 1783-1794 (2013) - [j11]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin
A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS. IEEE J. Solid State Circuits 48(9): 2154-2169 (2013) - [c37]Yun Du, Tao He, Yang Jiang
A continuous-time VCO-assisted VCO-based ΣΔ modulator with 76.6dB SNDR and 10MHz BW. ISCAS 2013: 373-376 - [c36]Wen-Lan Wu, Yan Zhu, Li Ding, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin
A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS. ISCAS 2013: 2239-2242 - [c35]Li Ding, Sai-Weng Sin
A background gain- calibration technique for low voltage pipelined ADCs based on nonlinear interpolation. MWSCAS 2013: 665-668 - 2012
- [j10]Yan Zhu, Chi-Hang Chan, Sai-Weng Sin
A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation. IEEE J. Solid State Circuits 47(11): 2614-2626 (2012) - [j9]He Gong Wei, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin
An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC. IEEE J. Solid State Circuits 47(11): 2763-2772 (2012) - [c34]Yun Du, Tao He, Yang Jiang
A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators. APCCAS 2012: 29-32 - [c33]Tao He, Yun Du, Yang Jiang
A DT 0-2 MASH ΣΔ modulator with VCO-based quantizer for enhanced linearity. APCCAS 2012: 33-36 - [c32]Wen-Lan Wu, Sai-Weng Sin
A 10-bit SAR ADC with two redundant decisions and splitted-MSB-cap DAC array. APCCAS 2012: 268-271 - [c31]Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin
A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC. CICC 2012: 1-4 - [c30]Rui Wang, U-Fat Chio, Sai-Weng Sin
A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique. ESSCIRC 2012: 265-268 - [c29]Guohe Yin, He Gong Wei, U-Fat Chio, Sai-Weng Sin
A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS. ESSCIRC 2012: 377-380 - [c28]Tao He, Yang Jiang
A 10MHz BW 78dB DR CT ΣΔ modulator with novel switched high linearity VCO-based quantizer. ISCAS 2012: 65-68 - [c27]Chen-Yan Cai, Yang Jiang
An ELD tracking compensation technique for active-RC CT ΣΔ modulators. MWSCAS 2012: 1096-1099 - [c26]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin
A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure. VLSIC 2012: 86-87 - [c25]Yan Zhu, Chi-Hang Chan, Sai-Weng Sin
A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC. VLSIC 2012: 90-91 - 2011
- [c24]Yan Zhu, Chi-Hang Chan, Sai-Weng Sin
A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation. A-SSCC 2011: 61-64 - [c23]Si-Seng Wong, U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin
A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators. A-SSCC 2011: 73-76 - [c22]Chi-Hang Chan, Yan Zhu, U. Fat Chio, Sai-Weng Sin
A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS. A-SSCC 2011: 233-236 - [c21]U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin
A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration. ESSCIRC 2011: 363-366 - [c20]Arshad Hussain, Sai-Weng Sin
Hybrid loopfilter sigma-delta modulator with NTF zero compensation. ISOCC 2011: 76-79 - [c19]He Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin
A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS. ISSCC 2011: 188-190 - 2010
- [j8]Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
1.2-V, 10-bit, 60-360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 μm CMOS with minimised supply headroom. IET Circuits Devices Syst. 4(1): 1-13 (2010) - [j7]Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS. IEEE J. Solid State Circuits 45(6): 1111-1121 (2010) - [j6]He Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin
A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 57-II(1): 16-20 (2010) - [j5]U-Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin
Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC. IEEE Trans. Circuits Syst. II Express Briefs 57-II(8): 607-611 (2010) - [j4]Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin
Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs. VLSI Design 2010: 706548:1-706548:8 (2010) - [c18]Li Ding, Sai-Weng Sin
An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs. APCCAS 2010: 208-211 - [c17]Yang Jiang
A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators. APCCAS 2010: 1011-1014 - [c16]Sai-Weng Sin
An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H. ESSCIRC 2010: 218-221 - [c15]Yang Jiang
A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators. ICECS 2010: 547-550 - [c14]Guohe Yin, U. Fat Chio, He Gong Wei, Sai-Weng Sin
An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications. ICECS 2010: 878-881 - [c13]Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin
A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs. ISCAS 2010: 4061-4064
2000 – 2009
- 2008
- [j3]Sai-Weng Sin
Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch. IEEE Trans. Circuits Syst. II Express Briefs 55-II(7): 648-652 (2008) - [j2]Sai-Weng Sin
Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(8): 2188-2201 (2008) - [c12]Li Ding, Sio Chan, Kim-Fai Wong, Sai-Weng Sin
A pseudo-differential comparator-based pipelined ADC with common mode feedforward technique. APCCAS 2008: 276-279 - [c11]U. Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin
A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs. APCCAS 2008: 1164-1167 - [c10]He Gong Wei, U. Fat Chio, Yan Zhu, Sai-Weng Sin
A process- and temperature- insensitive current-controlled delay generator for sampled-data systems. APCCAS 2008: 1192-1195 - [c9]Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin
A power-efficient capacitor structure for high-speed charge recycling SAR ADCs. ICECS 2008: 642-645 - [c8]He Gong Wei, U. Fat Chio, Sai-Weng Sin
A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier. ISCAS 2008: 5-8 - 2006
- [c7]Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications. ISCAS 2006 - [c6]Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits. ISCAS 2006 - 2005
- [c5]Sai-Weng Sin
A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits. ISCAS (2) 2005: 1581-1584 - [c4]Sai-Weng Sin
A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits. ISCAS (2) 2005: 1585-1588 - 2004
- [j1]Seng-Pan U., Sai-Weng Sin
Exact spectra analysis of sampled signals with jitter-induced nonuniformly holding effects. IEEE Trans. Instrum. Meas. 53(4): 1279-1288 (2004) - [c3]Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems. ISCAS (1) 2004: 369-372 - 2003
- [c2]Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
Quantitative noise analysis of jitter-induced nonuniformly sampled-and-held signals. ICASSP (6) 2003: 253-256 - [c1]Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, José E. Franca:
Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output. ISCAS (1) 2003: 129-132
Coauthor Index
U. Fat Chio
aka: U-Fat Chio
aka: U-Fat Chio
Rui Paulo Martins
aka: Rui Paulo da Silva Martins
aka: Rui Paulo da Silva Martins
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[j37] [j34] [c57] [c56] [j32] [c49] [j27] [j26] [j25] [j24] [j23] [j22] [j21] [j20] [c48] [c47] [c46] [j19] [j18] [j17] [j16] [c45] [c44] [c42] [j14] [c41] [c40] [c39] [j13] [c38] [j12] [j11] [c37] [c36] [c35] [j10] [j9] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [j8] [j7] [j6] [j5] [j4] [c18] [c17] [c16] [c15] [c14] [c13] [j3] [j2] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [j1] [c3] [c2] [c1]
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