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Wenning Jiang
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2020 – today
- 2024
- [c9]Wenning Jiang, Yunbin Luo, Peizhe Li, Ji Guo, Chixiao Chen, Qi Liu:
A 13b 500MS/s Dual-Residue Pipelined-SAR ADC with One-Way Switching Capacitive Interpolation and Background Offset Calibration. CICC 2024: 1-2 - [c8]Handa Sun, Zhaori Bi, Wenning Jiang, Ye Lu, Changhao Yan, Fan Yang, Wenchuang Hu, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
EVDMARL: Efficient Value Decomposition-based Multi-Agent Reinforcement Learning with Domain-Randomization for Complex Analog Circuit Design Migration. DAC 2024: 284:1-284:6 - 2023
- [j5]Wenning Jiang, Yan Zhu
, Chixiao Chen
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier. IEEE J. Solid State Circuits 58(10): 2709-2721 (2023) - [c7]Jie Liao, Bo Jiao, Jinshan Zhang, Shiwei Liu, Hao Jiang, Jun Tao, Wenning Jiang, Qi Liu, Lihua Zhang, Haozhe Zhu, Chixiao Chen:
A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration. ISCAS 2023: 1-5 - [c6]Chuang Wang
A Modified Two-Stage Cascaded Hybrid Converter with Reduced Conduction Loss, Self-Balanced Flying Capacitors and Simplified Interleaving PWM. ISCAS 2023: 1-5 - [c5]Chuang Wang
A Modified Interleaving Resonant Switched Capacitor Converter with Reduced Output Resistance and In-Situ Startup. ISCAS 2023: 1-4 - [c4]Xinsheng Wang, Maosong Shi, Peizhe Li, Jianwei Liu, Zhangcheng Huang
A 10b 1.25GS/s Residue Post-Amplified Pipelined-SAR ADC with Supply-and-Temperature Stabilized Open-Loop Residue Amplifier. ISCAS 2023: 1-5 - [c3]Shiwei Liu, Peizhe Li, Jinshan Zhang, Yunzhengmao Wang
A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine. ISSCC 2023: 250-251 - 2022
- [j4]Danfeng Zhai
High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4944-4957 (2022) - 2021
- [j3]Wenning Jiang
A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 557-568 (2021) - 2020
- [j2]Wenning Jiang
A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier. IEEE J. Solid State Circuits 55(2): 322-332 (2020)
2010 – 2019
- 2019
- [c2]Wenning Jiang
A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier. ISSCC 2019: 60-62 - 2018
- [c1]Wenning Jiang
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler. A-SSCC 2018: 235-238
2000 – 2009
- 2005
- [j1]Wenning Jiang, Jianping Chen, Junhe Zhou:
Optimal Position of Isolator to Suppress Double Rayleigh Backscattering Noise in Fiber Raman Amplifiers. IEICE Trans. Electron. 88-C(4): 721-724 (2005)
Coauthor Index
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