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Hao Xu 0005
Person information
- affiliation: University of California at Los Angeles, Electrical Engineering Department, CA, USA
Other persons with the same name
- Hao Xu — disambiguation page
- Hao Xu 0001
— Lucent Technol. Bell Labs., Holmdel, NJ, USA (and 1 more)
- Hao Xu 0002
- Hao Xu 0003
- Hao Xu 0004
- Hao Xu 0006 — University of North Carolina at Chapel Hill, DICE Center, NC, USA
- Hao Xu 0007
- Hao Xu 0008
- Hao Xu 0009
- Hao Xu 0010 — University of Cincinnati, School of Electronics and Computing Systems, OH, USA
- Hao Xu 0011 — University of North Carolina, Chapel Hill, USA
- Hao Xu 0012
- Hao Xu 0013
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2020 – today
- 2024
- [j8]Yan Liu
A 10-bit 563-fs Step Constant-Slope Digital-to-Time Converter in 40-nm CMOS With Nonlinearity Cancellation and Range Extension Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 71(2): 526-536 (2024) - [j7]Hao Xu
Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur. IEEE Trans. Circuits Syst. I Regul. Pap. 71(8): 3597-3607 (2024) - [c11]Yizhuo Wang, Hao Xu, Guoyu Li, Shuai Liu, Yan Liu, Rui Yin, Hui Pan, Na Yan:
An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOS. CICC 2024: 1-2 - [c10]Hao Xu, Junyan Bi, Tenghao Zou, Weitao He, Yaxin Zeng, Junjie Gu, Ziyang Jiao, Shubin Liu, Zhangming Zhu, Na Yan:
5.1 A 5-to-16GHz Reconfigurable Quadrature Receiver with 50% Duty-Cycle LO and IQ-Leakage Suppression. ISSCC 2024: 88-90 - 2023
- [j6]Yizhuo Wang, Jiahe Shi
Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL. IEEE J. Solid State Circuits 58(8): 2252-2266 (2023) - [j5]Wenning Jiang, Yan Zhu
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier. IEEE J. Solid State Circuits 58(10): 2709-2721 (2023) - [j4]Tenghao Zou
A 6-12 GHz Wideband Low-Noise Amplifier With 0.8-1.5 dB NF and ±0.75 dB Ripple Enabled by the Capacitor Assisting Triple-Winding Transformer. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 2802-2813 (2023) - [c9]Xinyi Lin, Hao Xu, Dejian Li, Na Yan:
A High Speed, Low Power and Low Phase Noise Divider for Wideband Application. ASICON 2023: 1-4 - [c8]Yiyun Mao, Haoyuan Gao, Dejian Li, Hao Xu, Na Yan:
An ADPLL Design Model Based on LoRa IoT Application. ASICON 2023: 1-4 - [c7]Peifang Wu, Yan Liu, Xi Feng, Hao Xu, Na Yan:
A Vernier Time-to-Digital Converter with 1.5ps Resolution for an All-Digital Phase Locked Loop in 28nm CMOS. ASICON 2023: 1-4 - [c6]Yaxin Zeng, Hao Xu, Xi Feng, Na Yan:
Analysis and Modeling of Non-ideal Effects in SAR ADC. ASICON 2023: 1-4 - 2022
- [c5]Jialong Xue, Tenghao Zou, Hao Xu, Tingting Han, Mi Tian, Weiqiang Zhu, Zhijian Li, Na Yan:
A 6-18GHz Low-Noise Amplifier Using Noise Canceling Technique in 130-nm CMOS PD-SOI. ICTA 2022: 46-47 - 2021
- [c4]Tetsuya Iizuka, Hao Xu, Asad A. Abidi:
A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW. ESSCIRC 2021: 381-386
2010 – 2019
- 2019
- [j3]Hao Xu
Analysis and Design of Regenerative Comparators for Low Offset and Noise. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 2817-2830 (2019) - [c3]Dihang Yang, Asad A. Abidi, Hooman Darabi, Hao Xu, David Murphy, Hao Wu, Zhaowen Wang
A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and-70dBc Fractional Spurs. ISSCC 2019: 266-268 - 2017
- [j2]Hao Xu
Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(7): 1637-1650 (2017) - 2015
- [j1]David Murphy, Hooman Darabi, Hao Xu:
A Noise-Cancelling Receiver Resilient to Large Harmonic Blockers. IEEE J. Solid State Circuits 50(6): 1336-1350 (2015) - 2014
- [c2]Asad A. Abidi, Hao Xu:
Understanding the regenerative comparator circuit. CICC 2014: 1-8 - [c1]David Murphy, Hooman Darabi, Hao Xu:
3.6 A noise-cancelling receiver with enhanced resilience to harmonic blockers. ISSCC 2014: 68-69
Coauthor Index
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